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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <platform.h>
33
34
35 .globl pcpu_dv_mem_stack
36 .weak platform_get_core_pos
37 .weak platform_set_stack
Achin Guptac8afc782013-11-25 18:45:02 +000038 .weak platform_get_stack
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 .weak platform_is_primary_cpu
40 .weak platform_set_coherent_stack
41 .weak platform_check_mpidr
42 .weak plat_report_exception
43
44 /* -----------------------------------------------------
45 * 512 bytes of coherent stack for each cpu
46 * -----------------------------------------------------
47 */
48#define PCPU_DV_MEM_STACK_SIZE 0x200
49
50
51 .section .text, "ax"; .align 3
52
53 /* -----------------------------------------------------
54 * unsigned long long platform_set_coherent_stack
55 * (unsigned mpidr);
56 * For a given mpidr, this function returns the stack
57 * pointer allocated in device memory. This stack can
58 * be used by C code which enables/disables the SCTLR.M
59 * SCTLR.C bit e.g. while powering down a cpu
60 * -----------------------------------------------------
61 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +000062platform_set_coherent_stack: ; .type platform_set_coherent_stack, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +010063 mov x5, x30 // lr
64 bl platform_get_core_pos
65 add x0, x0, #1
66 mov x1, #PCPU_DV_MEM_STACK_SIZE
67 mul x0, x0, x1
68 ldr x1, =pcpu_dv_mem_stack
69 add sp, x1, x0
70 ret x5
71
72
73 /* -----------------------------------------------------
74 * int platform_get_core_pos(int mpidr);
75 * With this function: CorePos = (ClusterId * 4) +
76 * CoreId
77 * -----------------------------------------------------
78 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +000079platform_get_core_pos: ; .type platform_get_core_pos, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +010080 and x1, x0, #MPIDR_CPU_MASK
81 and x0, x0, #MPIDR_CLUSTER_MASK
82 add x0, x1, x0, LSR #6
83 ret
84
85
86 /* -----------------------------------------------------
87 * void platform_is_primary_cpu (unsigned int mpid);
88 *
89 * Given the mpidr say whether this cpu is the primary
90 * cpu (applicable ony after a cold boot)
91 * -----------------------------------------------------
92 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +000093platform_is_primary_cpu: ; .type platform_is_primary_cpu, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +010094 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
95 cmp x0, #PRIMARY_CPU
96 cset x0, eq
97 ret
98
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 /* -----------------------------------------------------
Achin Guptac8afc782013-11-25 18:45:02 +0000100 * void platform_get_stack (unsigned long mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101 * -----------------------------------------------------
102 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000103platform_get_stack: ; .type platform_get_stack, %function
Achin Guptac8afc782013-11-25 18:45:02 +0000104 mov x10, x30 // lr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 bl platform_get_core_pos
106 add x0, x0, #1
107 mov x1, #PLATFORM_STACK_SIZE
108 mul x0, x0, x1
109 ldr x1, =platform_normal_stacks
Achin Guptac8afc782013-11-25 18:45:02 +0000110 add x0, x1, x0
111 ret x10
112
113 /* -----------------------------------------------------
114 * void platform_set_stack (unsigned long mpidr)
115 * -----------------------------------------------------
116 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000117platform_set_stack: ; .type platform_set_stack, %function
Achin Guptac8afc782013-11-25 18:45:02 +0000118 mov x9, x30 // lr
119 bl platform_get_stack
120 mov sp, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 ret x9
122
123 /* -----------------------------------------------------
124 * Placeholder function which should be redefined by
125 * each platform.
126 * -----------------------------------------------------
127 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000128platform_check_mpidr: ; .type platform_check_mpidr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129 mov x0, xzr
130 ret
131
132 /* -----------------------------------------------------
133 * Placeholder function which should be redefined by
134 * each platform.
135 * -----------------------------------------------------
136 */
137plat_report_exception:
138 ret
139
140 /* -----------------------------------------------------
141 * Per-cpu stacks in device memory.
142 * Used for C code just before power down or right after
143 * power up when the MMU or caches need to be turned on
144 * or off. Each cpu gets a stack of 512 bytes.
145 * -----------------------------------------------------
146 */
147 .section tzfw_coherent_mem, "aw", %nobits; .align 6
148
149pcpu_dv_mem_stack:
150 /* Zero fill */
151 .space (PLATFORM_CORE_COUNT * PCPU_DV_MEM_STACK_SIZE), 0