| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <platform.h> |
| 33 | |
| 34 | |
| 35 | .globl pcpu_dv_mem_stack |
| 36 | .weak platform_get_core_pos |
| 37 | .weak platform_set_stack |
| 38 | .weak platform_is_primary_cpu |
| 39 | .weak platform_set_coherent_stack |
| 40 | .weak platform_check_mpidr |
| 41 | .weak plat_report_exception |
| 42 | |
| 43 | /* ----------------------------------------------------- |
| 44 | * 512 bytes of coherent stack for each cpu |
| 45 | * ----------------------------------------------------- |
| 46 | */ |
| 47 | #define PCPU_DV_MEM_STACK_SIZE 0x200 |
| 48 | |
| 49 | |
| 50 | .section .text, "ax"; .align 3 |
| 51 | |
| 52 | /* ----------------------------------------------------- |
| 53 | * unsigned long long platform_set_coherent_stack |
| 54 | * (unsigned mpidr); |
| 55 | * For a given mpidr, this function returns the stack |
| 56 | * pointer allocated in device memory. This stack can |
| 57 | * be used by C code which enables/disables the SCTLR.M |
| 58 | * SCTLR.C bit e.g. while powering down a cpu |
| 59 | * ----------------------------------------------------- |
| 60 | */ |
| 61 | platform_set_coherent_stack:; .type platform_set_coherent_stack, %function |
| 62 | mov x5, x30 // lr |
| 63 | bl platform_get_core_pos |
| 64 | add x0, x0, #1 |
| 65 | mov x1, #PCPU_DV_MEM_STACK_SIZE |
| 66 | mul x0, x0, x1 |
| 67 | ldr x1, =pcpu_dv_mem_stack |
| 68 | add sp, x1, x0 |
| 69 | ret x5 |
| 70 | |
| 71 | |
| 72 | /* ----------------------------------------------------- |
| 73 | * int platform_get_core_pos(int mpidr); |
| 74 | * With this function: CorePos = (ClusterId * 4) + |
| 75 | * CoreId |
| 76 | * ----------------------------------------------------- |
| 77 | */ |
| 78 | platform_get_core_pos:; .type platform_get_core_pos, %function |
| 79 | and x1, x0, #MPIDR_CPU_MASK |
| 80 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 81 | add x0, x1, x0, LSR #6 |
| 82 | ret |
| 83 | |
| 84 | |
| 85 | /* ----------------------------------------------------- |
| 86 | * void platform_is_primary_cpu (unsigned int mpid); |
| 87 | * |
| 88 | * Given the mpidr say whether this cpu is the primary |
| 89 | * cpu (applicable ony after a cold boot) |
| 90 | * ----------------------------------------------------- |
| 91 | */ |
| 92 | platform_is_primary_cpu:; .type platform_is_primary_cpu, %function |
| 93 | and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
| 94 | cmp x0, #PRIMARY_CPU |
| 95 | cset x0, eq |
| 96 | ret |
| 97 | |
| 98 | |
| 99 | /* ----------------------------------------------------- |
| 100 | * void platform_set_stack (int mpidr) |
| 101 | * ----------------------------------------------------- |
| 102 | */ |
| 103 | platform_set_stack:; .type platform_set_stack, %function |
| 104 | mov x9, x30 // lr |
| 105 | bl platform_get_core_pos |
| 106 | add x0, x0, #1 |
| 107 | mov x1, #PLATFORM_STACK_SIZE |
| 108 | mul x0, x0, x1 |
| 109 | ldr x1, =platform_normal_stacks |
| 110 | add sp, x1, x0 |
| 111 | ret x9 |
| 112 | |
| 113 | /* ----------------------------------------------------- |
| 114 | * Placeholder function which should be redefined by |
| 115 | * each platform. |
| 116 | * ----------------------------------------------------- |
| 117 | */ |
| 118 | platform_check_mpidr:; .type platform_check_mpidr, %function |
| 119 | mov x0, xzr |
| 120 | ret |
| 121 | |
| 122 | /* ----------------------------------------------------- |
| 123 | * Placeholder function which should be redefined by |
| 124 | * each platform. |
| 125 | * ----------------------------------------------------- |
| 126 | */ |
| 127 | plat_report_exception: |
| 128 | ret |
| 129 | |
| 130 | /* ----------------------------------------------------- |
| 131 | * Per-cpu stacks in device memory. |
| 132 | * Used for C code just before power down or right after |
| 133 | * power up when the MMU or caches need to be turned on |
| 134 | * or off. Each cpu gets a stack of 512 bytes. |
| 135 | * ----------------------------------------------------- |
| 136 | */ |
| 137 | .section tzfw_coherent_mem, "aw", %nobits; .align 6 |
| 138 | |
| 139 | pcpu_dv_mem_stack: |
| 140 | /* Zero fill */ |
| 141 | .space (PLATFORM_CORE_COUNT * PCPU_DV_MEM_STACK_SIZE), 0 |