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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Arm Fixed Virtual Platforms (FVP)
2=================================
3
4Fixed Virtual Platform (FVP) Support
5------------------------------------
6
7This section lists the supported Arm |FVP| platforms. Please refer to the FVP
8documentation for a detailed description of the model parameter options.
9
10The latest version of the AArch64 build of TF-A has been tested on the following
11Arm FVPs without shifted affinities, and that do not support threaded CPU cores
12(64-bit host machine only).
13
14.. note::
Maksims Svecovsfd115b62021-10-25 16:13:42 +010015 The FVP models used are Version 11.16 Build 16, unless otherwise stated.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010016
Maksims Svecovsfd115b62021-10-25 16:13:42 +010017- ``Foundation_Platform``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010018- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
Maksims Svecovsfd115b62021-10-25 16:13:42 +010019- ``FVP_Base_AEMv8A-AEMv8A`` (For certain configurations also uses 11.14/21)
20- ``FVP_Base_AEMv8A-GIC600AE``
21- ``FVP_Base_AEMvA`` (For certain configurations also uses 0.0/6684)
22- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010023- ``FVP_Base_Cortex-A35x4``
24- ``FVP_Base_Cortex-A53x4``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010025- ``FVP_Base_Cortex-A55x4``
Maksims Svecovsfd115b62021-10-25 16:13:42 +010026- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010027- ``FVP_Base_Cortex-A57x1-A53x1``
28- ``FVP_Base_Cortex-A57x2-A53x4``
29- ``FVP_Base_Cortex-A57x4-A53x4``
30- ``FVP_Base_Cortex-A57x4``
laurenw-arm0a9b8d02020-04-15 17:48:36 -050031- ``FVP_Base_Cortex-A65AEx8``
Maksims Svecovsfd115b62021-10-25 16:13:42 +010032- ``FVP_Base_Cortex-A65x4``
33- ``FVP_Base_Cortex-A710x4``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010034- ``FVP_Base_Cortex-A72x4-A53x4``
35- ``FVP_Base_Cortex-A72x4``
36- ``FVP_Base_Cortex-A73x4-A53x4``
37- ``FVP_Base_Cortex-A73x4``
38- ``FVP_Base_Cortex-A75x4``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``FVP_Base_Cortex-A76AEx4``
40- ``FVP_Base_Cortex-A76AEx8``
Maksims Svecovsfd115b62021-10-25 16:13:42 +010041- ``FVP_Base_Cortex-A76x4``
laurenw-arm0a9b8d02020-04-15 17:48:36 -050042- ``FVP_Base_Cortex-A77x4``
Manish V Badarkhebfd177e2020-10-02 07:27:27 +010043- ``FVP_Base_Cortex-A78x4``
Alexei Fedorovd6781fb2020-07-20 13:26:49 +010044- ``FVP_Base_Neoverse-E1x1``
45- ``FVP_Base_Neoverse-E1x2``
46- ``FVP_Base_Neoverse-E1x4``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010047- ``FVP_Base_Neoverse-N1x4``
laurenw-arm74d33382021-05-04 10:23:14 -050048- ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38)
Manish V Badarkhebfd177e2020-10-02 07:27:27 +010049- ``FVP_Base_Neoverse-V1x4``
Maksims Svecovsfd115b62021-10-25 16:13:42 +010050- ``FVP_Base_RevC-2xAEMvA`` (For certain configurations also uses 0.0/6557)
51- ``FVP_CSS_SGI-575`` (Version 11.15/26)
52- ``FVP_Morello`` (Version 0.11/19)
53- ``FVP_RD_E1_edge`` (Version 11.15/26)
54- ``FVP_RD_N1_edge_dual`` (Version 11.15/26)
55- ``FVP_RD_N1_edge`` (Version 11.15/26)
56- ``FVP_RD_V1`` (Version 11.15/26)
57- ``FVP_TC0``
58- ``FVP_TC1``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010059
60The latest version of the AArch32 build of TF-A has been tested on the
61following Arm FVPs without shifted affinities, and that do not support threaded
62CPU cores (64-bit host machine only).
63
Manish V Badarkhebfd177e2020-10-02 07:27:27 +010064- ``FVP_Base_AEMvA``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010065- ``FVP_Base_AEMv8A-AEMv8A``
66- ``FVP_Base_Cortex-A32x4``
67
68.. note::
69 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
70 is not compatible with legacy GIC configurations. Therefore this FVP does not
71 support these legacy GIC configurations.
72
73The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
74FVP website`_. The Cortex-A models listed above are also available to download
75from `Arm's website`_.
76
77.. note::
78 The build numbers quoted above are those reported by launching the FVP
79 with the ``--version`` parameter.
80
81.. note::
82 Linaro provides a ramdisk image in prebuilt FVP configurations and full
83 file systems that can be downloaded separately. To run an FVP with a virtio
84 file system image an additional FVP configuration option
85 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
86 used.
87
88.. note::
89 The software will not work on Version 1.0 of the Foundation FVP.
90 The commands below would report an ``unhandled argument`` error in this case.
91
92.. note::
93 FVPs can be launched with ``--cadi-server`` option such that a
94 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
95 its execution.
96
97.. warning::
98 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
99 the internal synchronisation timings changed compared to older versions of
100 the models. The models can be launched with ``-Q 100`` option if they are
101 required to match the run time characteristics of the older versions.
102
Zelalemc005fdf2021-06-01 17:05:16 -0500103All the above platforms have been tested with `Linaro Release 20.01`_.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100104
105.. _build_options_arm_fvp_platform:
106
107Arm FVP Platform Specific Build Options
108---------------------------------------
109
110- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
111 build the topology tree within TF-A. By default TF-A is configured for dual
112 cluster topology and this option can be used to override the default value.
113
114- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
115 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
116 explained in the options below:
117
118 - ``FVP_CCI`` : The CCI driver is selected. This is the default
119 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
120 - ``FVP_CCN`` : The CCN driver is selected. This is the default
121 if ``FVP_CLUSTER_COUNT`` > 2.
122
123- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
124 a single cluster. This option defaults to 4.
125
126- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
127 in the system. This option defaults to 1. Note that the build option
128 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
129
130- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
131
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100132 - ``FVP_GICV2`` : The GICv2 only driver is selected
133 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
134
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100135- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
136 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
137 details on HW_CONFIG. By default, this is initialized to a sensible DTS
138 file in ``fdts/`` folder depending on other build options. But some cases,
139 like shifted affinity format for MPIDR, cannot be detected at build time
140 and this option is needed to specify the appropriate DTS file.
141
142- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
143 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
144 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
145 HW_CONFIG blob instead of the DTS file. This option is useful to override
146 the default HW_CONFIG selected by the build system.
147
Manish V Badarkhe2f4c0442021-01-24 20:39:39 +0000148- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
149 inactive/fused CPU cores as read-only. The default value of this option
150 is ``0``, which means the redistributor pages of all CPU cores are marked
151 as read and write.
152
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100153Booting Firmware Update images
154------------------------------
155
156When Firmware Update (FWU) is enabled there are at least 2 new images
157that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
158FWU FIP.
159
160The additional fip images must be loaded with:
161
162::
163
164 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
165 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
166
167The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
168In the same way, the address ns_bl2u_base_address is the value of
169NS_BL2U_BASE.
170
171Booting an EL3 payload
172----------------------
173
174The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
175the secondary CPUs holding pen to work properly. Unfortunately, its reset value
176is undefined on the FVP platform and the FVP platform code doesn't clear it.
177Therefore, one must modify the way the model is normally invoked in order to
178clear the mailbox at start-up.
179
180One way to do that is to create an 8-byte file containing all zero bytes using
181the following command:
182
183.. code:: shell
184
185 dd if=/dev/zero of=mailbox.dat bs=1 count=8
186
187and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
188using the following model parameters:
189
190::
191
192 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
193 --data=mailbox.dat@0x04000000 [Foundation FVP]
194
195To provide the model with the EL3 payload image, the following methods may be
196used:
197
198#. If the EL3 payload is able to execute in place, it may be programmed into
199 flash memory. On Base Cortex and AEM FVPs, the following model parameter
200 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
201 used for the FIP):
202
203 ::
204
205 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
206
207 On Foundation FVP, there is no flash loader component and the EL3 payload
208 may be programmed anywhere in flash using method 3 below.
209
210#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
211 command may be used to load the EL3 payload ELF image over JTAG:
212
213 ::
214
215 load <path-to>/el3-payload.elf
216
217#. The EL3 payload may be pre-loaded in volatile memory using the following
218 model parameters:
219
220 ::
221
222 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
223 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
224
225 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
226 used when building TF-A.
227
228Booting a preloaded kernel image (Base FVP)
229-------------------------------------------
230
231The following example uses a simplified boot flow by directly jumping from the
232TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
233useful if both the kernel and the device tree blob (DTB) are already present in
234memory (like in FVP).
235
236For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
237address ``0x82000000``, the firmware can be built like this:
238
239.. code:: shell
240
Madhukar Pappireddyc0ba2482020-01-10 16:11:18 -0600241 CROSS_COMPILE=aarch64-none-elf- \
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100242 make PLAT=fvp DEBUG=1 \
243 RESET_TO_BL31=1 \
244 ARM_LINUX_KERNEL_AS_BL33=1 \
245 PRELOADED_BL33_BASE=0x80080000 \
246 ARM_PRELOADED_DTB_BASE=0x82000000 \
247 all fip
248
249Now, it is needed to modify the DTB so that the kernel knows the address of the
250ramdisk. The following script generates a patched DTB from the provided one,
251assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
252script assumes that the user is using a ramdisk image prepared for U-Boot, like
253the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
254offset in ``INITRD_START`` has to be removed.
255
256.. code:: bash
257
258 #!/bin/bash
259
260 # Path to the input DTB
261 KERNEL_DTB=<path-to>/<fdt>
262 # Path to the output DTB
263 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
264 # Base address of the ramdisk
265 INITRD_BASE=0x84000000
266 # Path to the ramdisk
267 INITRD=<path-to>/<ramdisk.img>
268
269 # Skip uboot header (64 bytes)
270 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
271 INITRD_SIZE=$(stat -Lc %s ${INITRD})
272 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
273
274 CHOSEN_NODE=$(echo \
275 "/ { \
276 chosen { \
277 linux,initrd-start = <${INITRD_START}>; \
278 linux,initrd-end = <${INITRD_END}>; \
279 }; \
280 };")
281
282 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
283 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
284
285And the FVP binary can be run with the following command:
286
287.. code:: shell
288
289 <path-to>/FVP_Base_AEMv8A-AEMv8A \
290 -C pctl.startup=0.0.0.0 \
291 -C bp.secure_memory=1 \
292 -C cluster0.NUM_CORES=4 \
293 -C cluster1.NUM_CORES=4 \
294 -C cache_state_modelled=1 \
Alexei Fedorovea0424f2020-02-17 13:38:35 +0000295 -C cluster0.cpu0.RVBAR=0x04001000 \
296 -C cluster0.cpu1.RVBAR=0x04001000 \
297 -C cluster0.cpu2.RVBAR=0x04001000 \
298 -C cluster0.cpu3.RVBAR=0x04001000 \
299 -C cluster1.cpu0.RVBAR=0x04001000 \
300 -C cluster1.cpu1.RVBAR=0x04001000 \
301 -C cluster1.cpu2.RVBAR=0x04001000 \
302 -C cluster1.cpu3.RVBAR=0x04001000 \
303 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100304 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
305 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
306 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
307
308Obtaining the Flattened Device Trees
309^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
310
311Depending on the FVP configuration and Linux configuration used, different
312FDT files are required. FDT source files for the Foundation and Base FVPs can
313be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
314a subset of the Base FVP components. For example, the Foundation FVP lacks
315CLCD and MMC support, and has only one CPU cluster.
316
317.. note::
318 It is not recommended to use the FDTs built along the kernel because not
319 all FDTs are available from there.
320
321The dynamic configuration capability is enabled in the firmware for FVPs.
322This means that the firmware can authenticate and load the FDT if present in
323FIP. A default FDT is packaged into FIP during the build based on
324the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
325or ``FVP_HW_CONFIG_DTS`` build options (refer to
326:ref:`build_options_arm_fvp_platform` for details on the options).
327
328- ``fvp-base-gicv2-psci.dts``
329
330 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
331 affinities and with Base memory map configuration.
332
333- ``fvp-base-gicv2-psci-aarch32.dts``
334
335 For use with models such as the Cortex-A32 Base FVPs without shifted
336 affinities and running Linux in AArch32 state with Base memory map
337 configuration.
338
339- ``fvp-base-gicv3-psci.dts``
340
341 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
342 affinities and with Base memory map configuration and Linux GICv3 support.
343
344- ``fvp-base-gicv3-psci-1t.dts``
345
346 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
347 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
348
349- ``fvp-base-gicv3-psci-dynamiq.dts``
350
351 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
352 single cluster, single threaded CPUs, Base memory map configuration and Linux
353 GICv3 support.
354
355- ``fvp-base-gicv3-psci-aarch32.dts``
356
357 For use with models such as the Cortex-A32 Base FVPs without shifted
358 affinities and running Linux in AArch32 state with Base memory map
359 configuration and Linux GICv3 support.
360
361- ``fvp-foundation-gicv2-psci.dts``
362
363 For use with Foundation FVP with Base memory map configuration.
364
365- ``fvp-foundation-gicv3-psci.dts``
366
367 (Default) For use with Foundation FVP with Base memory map configuration
368 and Linux GICv3 support.
369
370
371Running on the Foundation FVP with reset to BL1 entrypoint
372^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
373
374The following ``Foundation_Platform`` parameters should be used to boot Linux with
3754 CPUs using the AArch64 build of TF-A.
376
377.. code:: shell
378
379 <path-to>/Foundation_Platform \
380 --cores=4 \
381 --arm-v8.0 \
382 --secure-memory \
383 --visualization \
384 --gicv3 \
385 --data="<path-to>/<bl1-binary>"@0x0 \
386 --data="<path-to>/<FIP-binary>"@0x08000000 \
387 --data="<path-to>/<kernel-binary>"@0x80080000 \
388 --data="<path-to>/<ramdisk-binary>"@0x84000000
389
390Notes:
391
392- BL1 is loaded at the start of the Trusted ROM.
393- The Firmware Image Package is loaded at the start of NOR FLASH0.
394- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
Manish V Badarkhe393caac2022-04-25 20:21:28 +0100395 is specified via the ``load-address`` property in the ``hw-config`` node of
396 `FW_CONFIG for FVP`_.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100397- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
398 and enable the GICv3 device in the model. Note that without this option,
399 the Foundation FVP defaults to legacy (Versatile Express) memory map which
400 is not supported by TF-A.
401- In order for TF-A to run correctly on the Foundation FVP, the architecture
402 versions must match. The Foundation FVP defaults to the highest v8.x
403 version it supports but the default build for TF-A is for v8.0. To avoid
404 issues either start the Foundation FVP to use v8.0 architecture using the
405 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
406 ``ARM_ARCH_MINOR``.
407
408Running on the AEMv8 Base FVP with reset to BL1 entrypoint
409^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
410
411The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
412with 8 CPUs using the AArch64 build of TF-A.
413
414.. code:: shell
415
416 <path-to>/FVP_Base_RevC-2xAEMv8A \
417 -C pctl.startup=0.0.0.0 \
418 -C bp.secure_memory=1 \
419 -C bp.tzc_400.diagnostics=1 \
420 -C cluster0.NUM_CORES=4 \
421 -C cluster1.NUM_CORES=4 \
422 -C cache_state_modelled=1 \
423 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
424 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
425 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
426 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
427
428.. note::
429 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
430 a specific DTS for all the CPUs to be loaded.
431
432Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
433^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
434
435The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
436with 8 CPUs using the AArch32 build of TF-A.
437
438.. code:: shell
439
440 <path-to>/FVP_Base_AEMv8A-AEMv8A \
441 -C pctl.startup=0.0.0.0 \
442 -C bp.secure_memory=1 \
443 -C bp.tzc_400.diagnostics=1 \
444 -C cluster0.NUM_CORES=4 \
445 -C cluster1.NUM_CORES=4 \
446 -C cache_state_modelled=1 \
447 -C cluster0.cpu0.CONFIG64=0 \
448 -C cluster0.cpu1.CONFIG64=0 \
449 -C cluster0.cpu2.CONFIG64=0 \
450 -C cluster0.cpu3.CONFIG64=0 \
451 -C cluster1.cpu0.CONFIG64=0 \
452 -C cluster1.cpu1.CONFIG64=0 \
453 -C cluster1.cpu2.CONFIG64=0 \
454 -C cluster1.cpu3.CONFIG64=0 \
455 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
456 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
457 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
458 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
459
460Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
461^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
462
463The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
464boot Linux with 8 CPUs using the AArch64 build of TF-A.
465
466.. code:: shell
467
468 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
469 -C pctl.startup=0.0.0.0 \
470 -C bp.secure_memory=1 \
471 -C bp.tzc_400.diagnostics=1 \
472 -C cache_state_modelled=1 \
473 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
474 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
475 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
476 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
477
478Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
479^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
480
481The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
482boot Linux with 4 CPUs using the AArch32 build of TF-A.
483
484.. code:: shell
485
486 <path-to>/FVP_Base_Cortex-A32x4 \
487 -C pctl.startup=0.0.0.0 \
488 -C bp.secure_memory=1 \
489 -C bp.tzc_400.diagnostics=1 \
490 -C cache_state_modelled=1 \
491 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
492 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
493 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
494 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
495
496
497Running on the AEMv8 Base FVP with reset to BL31 entrypoint
498^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
499
500The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
501with 8 CPUs using the AArch64 build of TF-A.
502
503.. code:: shell
504
505 <path-to>/FVP_Base_RevC-2xAEMv8A \
506 -C pctl.startup=0.0.0.0 \
507 -C bp.secure_memory=1 \
508 -C bp.tzc_400.diagnostics=1 \
509 -C cluster0.NUM_CORES=4 \
510 -C cluster1.NUM_CORES=4 \
511 -C cache_state_modelled=1 \
512 -C cluster0.cpu0.RVBAR=0x04010000 \
513 -C cluster0.cpu1.RVBAR=0x04010000 \
514 -C cluster0.cpu2.RVBAR=0x04010000 \
515 -C cluster0.cpu3.RVBAR=0x04010000 \
516 -C cluster1.cpu0.RVBAR=0x04010000 \
517 -C cluster1.cpu1.RVBAR=0x04010000 \
518 -C cluster1.cpu2.RVBAR=0x04010000 \
519 -C cluster1.cpu3.RVBAR=0x04010000 \
520 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
521 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
522 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
523 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
524 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
525 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
526
527Notes:
528
Manish Pandey928da862021-06-10 15:22:48 +0100529- Position Independent Executable (PIE) support is enabled in this
530 config allowing BL31 to be loaded at any valid address for execution.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100531
532- Since a FIP is not loaded when using BL31 as reset entrypoint, the
533 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
534 parameter is needed to load the individual bootloader images in memory.
535 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
536 Payload. For the same reason, the FDT needs to be compiled from the DT source
537 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
538 parameter.
539
540- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
541 specific DTS for all the CPUs to be loaded.
542
543- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
544 X and Y are the cluster and CPU numbers respectively, is used to set the
545 reset vector for each core.
546
547- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
548 changing the value of
549 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
550 ``BL32_BASE``.
551
552
553Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
554^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
555
556The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
557with 8 CPUs using the AArch32 build of TF-A.
558
559.. code:: shell
560
561 <path-to>/FVP_Base_AEMv8A-AEMv8A \
562 -C pctl.startup=0.0.0.0 \
563 -C bp.secure_memory=1 \
564 -C bp.tzc_400.diagnostics=1 \
565 -C cluster0.NUM_CORES=4 \
566 -C cluster1.NUM_CORES=4 \
567 -C cache_state_modelled=1 \
568 -C cluster0.cpu0.CONFIG64=0 \
569 -C cluster0.cpu1.CONFIG64=0 \
570 -C cluster0.cpu2.CONFIG64=0 \
571 -C cluster0.cpu3.CONFIG64=0 \
572 -C cluster1.cpu0.CONFIG64=0 \
573 -C cluster1.cpu1.CONFIG64=0 \
574 -C cluster1.cpu2.CONFIG64=0 \
575 -C cluster1.cpu3.CONFIG64=0 \
576 -C cluster0.cpu0.RVBAR=0x04002000 \
577 -C cluster0.cpu1.RVBAR=0x04002000 \
578 -C cluster0.cpu2.RVBAR=0x04002000 \
579 -C cluster0.cpu3.RVBAR=0x04002000 \
580 -C cluster1.cpu0.RVBAR=0x04002000 \
581 -C cluster1.cpu1.RVBAR=0x04002000 \
582 -C cluster1.cpu2.RVBAR=0x04002000 \
583 -C cluster1.cpu3.RVBAR=0x04002000 \
584 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
585 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
586 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
587 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
588 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
589
590.. note::
Manish Pandey928da862021-06-10 15:22:48 +0100591 Position Independent Executable (PIE) support is enabled in this
592 config allowing SP_MIN to be loaded at any valid address for execution.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100593
594Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
595^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
596
597The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
598boot Linux with 8 CPUs using the AArch64 build of TF-A.
599
600.. code:: shell
601
602 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
603 -C pctl.startup=0.0.0.0 \
604 -C bp.secure_memory=1 \
605 -C bp.tzc_400.diagnostics=1 \
606 -C cache_state_modelled=1 \
607 -C cluster0.cpu0.RVBARADDR=0x04010000 \
608 -C cluster0.cpu1.RVBARADDR=0x04010000 \
609 -C cluster0.cpu2.RVBARADDR=0x04010000 \
610 -C cluster0.cpu3.RVBARADDR=0x04010000 \
611 -C cluster1.cpu0.RVBARADDR=0x04010000 \
612 -C cluster1.cpu1.RVBARADDR=0x04010000 \
613 -C cluster1.cpu2.RVBARADDR=0x04010000 \
614 -C cluster1.cpu3.RVBARADDR=0x04010000 \
615 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
616 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
617 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
618 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
619 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
620 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
621
622Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
623^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
624
625The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
626boot Linux with 4 CPUs using the AArch32 build of TF-A.
627
628.. code:: shell
629
630 <path-to>/FVP_Base_Cortex-A32x4 \
631 -C pctl.startup=0.0.0.0 \
632 -C bp.secure_memory=1 \
633 -C bp.tzc_400.diagnostics=1 \
634 -C cache_state_modelled=1 \
635 -C cluster0.cpu0.RVBARADDR=0x04002000 \
636 -C cluster0.cpu1.RVBARADDR=0x04002000 \
637 -C cluster0.cpu2.RVBARADDR=0x04002000 \
638 -C cluster0.cpu3.RVBARADDR=0x04002000 \
639 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
640 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
641 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
642 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
643 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
644
645--------------
646
Manish V Badarkhe393caac2022-04-25 20:21:28 +0100647*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100648
Manish V Badarkhe393caac2022-04-25 20:21:28 +0100649.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100650.. _Arm's website: `FVP models`_
651.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Zelalemc005fdf2021-06-01 17:05:16 -0500652.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100653.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms