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Soby Mathewe063d3c2015-10-07 09:45:27 +01001/*
Roberto Vargas05712702018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewe063d3c2015-10-07 09:45:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewe063d3c2015-10-07 09:45:27 +01005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <debug.h>
11#include <gic_common.h>
12#include <gicv2.h>
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010013#include <interrupt_props.h>
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010014#include <spinlock.h>
Soby Mathew50f6fe42016-02-01 17:59:22 +000015#include "../common/gic_common_private.h"
Soby Mathewe063d3c2015-10-07 09:45:27 +010016#include "gicv2_private.h"
17
18static const gicv2_driver_data_t *driver_data;
19
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010020/*
21 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
24 */
Roberto Vargas05712702018-02-12 12:36:17 +000025static spinlock_t gic_lock;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010026
Soby Mathewe063d3c2015-10-07 09:45:27 +010027/*******************************************************************************
28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
29 * and set the priority mask register to allow all interrupts to trickle in.
30 ******************************************************************************/
31void gicv2_cpuif_enable(void)
32{
33 unsigned int val;
34
35 assert(driver_data);
36 assert(driver_data->gicc_base);
37
38 /*
39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1
40 * bypass.
41 */
42 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0;
43 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
44
45 /* Program the idle priority in the PMR */
46 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK);
47 gicc_write_ctlr(driver_data->gicc_base, val);
48}
49
50/*******************************************************************************
51 * Place the cpu interface in a state where it can never make a cpu exit wfi as
52 * as result of an asserted interrupt. This is critical for powering down a cpu
53 ******************************************************************************/
54void gicv2_cpuif_disable(void)
55{
56 unsigned int val;
57
58 assert(driver_data);
59 assert(driver_data->gicc_base);
60
61 /* Disable secure, non-secure interrupts and disable their bypass */
62 val = gicc_read_ctlr(driver_data->gicc_base);
63 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT);
64 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
65 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
66 gicc_write_ctlr(driver_data->gicc_base, val);
67}
68
69/*******************************************************************************
70 * Per cpu gic distributor setup which will be done by all cpus after a cold
71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them.
72 ******************************************************************************/
73void gicv2_pcpu_distif_init(void)
74{
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +000075 unsigned int ctlr;
76
Soby Mathewe063d3c2015-10-07 09:45:27 +010077 assert(driver_data);
78 assert(driver_data->gicd_base);
Soby Mathewe063d3c2015-10-07 09:45:27 +010079
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010080#if !ERROR_DEPRECATED
81 if (driver_data->interrupt_props != NULL) {
82#endif
83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
84 driver_data->interrupt_props,
85 driver_data->interrupt_props_num);
86#if !ERROR_DEPRECATED
87 } else {
Dan Handley4d408b52018-03-01 16:00:15 +000088 /*
89 * Suppress deprecated declaration warnings in compatibility
90 * function
91 */
92#pragma GCC diagnostic push
93#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010094 assert(driver_data->g0_interrupt_array);
95 gicv2_secure_ppi_sgi_setup(driver_data->gicd_base,
96 driver_data->g0_interrupt_num,
97 driver_data->g0_interrupt_array);
Dan Handley4d408b52018-03-01 16:00:15 +000098#pragma GCC diagnostic pop
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010099 }
100#endif
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000101
102 /* Enable G0 interrupts if not already */
103 ctlr = gicd_read_ctlr(driver_data->gicd_base);
104 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) {
105 gicd_write_ctlr(driver_data->gicd_base,
106 ctlr | CTLR_ENABLE_G0_BIT);
107 }
Soby Mathewe063d3c2015-10-07 09:45:27 +0100108}
109
110/*******************************************************************************
111 * Global gic distributor init which will be done by the primary cpu after a
112 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
113 * then enables the secure GIC distributor interface.
114 ******************************************************************************/
115void gicv2_distif_init(void)
116{
117 unsigned int ctlr;
118
119 assert(driver_data);
120 assert(driver_data->gicd_base);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100121
122 /* Disable the distributor before going further */
123 ctlr = gicd_read_ctlr(driver_data->gicd_base);
124 gicd_write_ctlr(driver_data->gicd_base,
125 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT));
126
127 /* Set the default attribute of all SPIs */
128 gicv2_spis_configure_defaults(driver_data->gicd_base);
129
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100130#if !ERROR_DEPRECATED
131 if (driver_data->interrupt_props != NULL) {
132#endif
133 gicv2_secure_spis_configure_props(driver_data->gicd_base,
134 driver_data->interrupt_props,
135 driver_data->interrupt_props_num);
136#if !ERROR_DEPRECATED
137 } else {
Dan Handley4d408b52018-03-01 16:00:15 +0000138 /*
139 * Suppress deprecated declaration warnings in compatibility
140 * function
141 */
142#pragma GCC diagnostic push
143#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
144
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100145 assert(driver_data->g0_interrupt_array);
146
147 /* Configure the G0 SPIs */
148 gicv2_secure_spis_configure(driver_data->gicd_base,
149 driver_data->g0_interrupt_num,
150 driver_data->g0_interrupt_array);
Dan Handley4d408b52018-03-01 16:00:15 +0000151#pragma GCC diagnostic pop
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100152 }
153#endif
Soby Mathewe063d3c2015-10-07 09:45:27 +0100154
155 /* Re-enable the secure SPIs now that they have been configured */
156 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT);
157}
158
159/*******************************************************************************
160 * Initialize the ARM GICv2 driver with the provided platform inputs
161 ******************************************************************************/
162void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
163{
164 unsigned int gic_version;
165 assert(plat_driver_data);
166 assert(plat_driver_data->gicd_base);
167 assert(plat_driver_data->gicc_base);
168
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100169#if !ERROR_DEPRECATED
170 if (plat_driver_data->interrupt_props == NULL) {
171 /* Interrupt properties array size must be 0 */
172 assert(plat_driver_data->interrupt_props_num == 0);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100173
Dan Handley4d408b52018-03-01 16:00:15 +0000174 /*
175 * Suppress deprecated declaration warnings in compatibility
176 * function
177 */
178#pragma GCC diagnostic push
179#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
180
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100181 /* The platform should provide a list of secure interrupts */
182 assert(plat_driver_data->g0_interrupt_array);
183
184 /*
185 * If there are no interrupts of a particular type, then the
186 * number of interrupts of that type should be 0 and vice-versa.
187 */
188 assert(plat_driver_data->g0_interrupt_array ?
189 plat_driver_data->g0_interrupt_num :
190 plat_driver_data->g0_interrupt_num == 0);
Dan Handley4d408b52018-03-01 16:00:15 +0000191#pragma GCC diagnostic pop
192
193 WARN("Using deprecated integer interrupt array in "
194 "gicv2_driver_data_t\n");
195 WARN("Please migrate to using an interrupt_prop_t array\n");
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100196 }
197#else
198 assert(plat_driver_data->interrupt_props != NULL);
199 assert(plat_driver_data->interrupt_props_num > 0);
200#endif
Soby Mathewe063d3c2015-10-07 09:45:27 +0100201
202 /* Ensure that this is a GICv2 system */
203 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
204 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT)
205 & PIDR2_ARCH_REV_MASK;
Etienne Carriere0a8c3532017-11-05 22:57:38 +0100206
207 /*
208 * GICv1 with security extension complies with trusted firmware
209 * GICv2 driver as far as virtualization and few tricky power
210 * features are not used. GICv2 features that are not supported
211 * by GICv1 with Security Extensions are:
212 * - virtual interrupt support.
213 * - wake up events.
214 * - writeable GIC state register (for power sequences)
215 * - interrupt priority drop.
216 * - interrupt signal bypass.
217 */
218 assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100219
220 driver_data = plat_driver_data;
221
Soby Mathew72645132017-02-14 10:11:52 +0000222 /*
223 * The GIC driver data is initialized by the primary CPU with caches
224 * enabled. When the secondary CPU boots up, it initializes the
225 * GICC/GICR interface with the caches disabled. Hence flush the
226 * driver_data to ensure coherency. This is not required if the
227 * platform has HW_ASSISTED_COHERENCY enabled.
228 */
229#if !HW_ASSISTED_COHERENCY
230 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
231 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
232#endif
Soby Mathewe063d3c2015-10-07 09:45:27 +0100233 INFO("ARM GICv2 driver initialized\n");
234}
235
236/******************************************************************************
237 * This function returns whether FIQ is enabled in the GIC CPU interface.
238 *****************************************************************************/
239unsigned int gicv2_is_fiq_enabled(void)
240{
241 unsigned int gicc_ctlr;
242
243 assert(driver_data);
244 assert(driver_data->gicc_base);
245
246 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base);
247 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1;
248}
249
250/*******************************************************************************
251 * This function returns the type of the highest priority pending interrupt at
252 * the GIC cpu interface. The return values can be one of the following :
253 * PENDING_G1_INTID : The interrupt type is non secure Group 1.
254 * 0 - 1019 : The interrupt type is secure Group 0.
255 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
256 * sufficient priority to be signaled
257 ******************************************************************************/
258unsigned int gicv2_get_pending_interrupt_type(void)
259{
260 assert(driver_data);
261 assert(driver_data->gicc_base);
262
263 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
264}
265
266/*******************************************************************************
267 * This function returns the id of the highest priority pending interrupt at
268 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no
269 * interrupt pending.
270 ******************************************************************************/
271unsigned int gicv2_get_pending_interrupt_id(void)
272{
273 unsigned int id;
274
275 assert(driver_data);
276 assert(driver_data->gicc_base);
277
278 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
279
280 /*
281 * Find out which non-secure interrupt it is under the assumption that
282 * the GICC_CTLR.AckCtl bit is 0.
283 */
284 if (id == PENDING_G1_INTID)
285 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK;
286
287 return id;
288}
289
290/*******************************************************************************
291 * This functions reads the GIC cpu interface Interrupt Acknowledge register
292 * to start handling the pending secure 0 interrupt. It returns the
293 * contents of the IAR.
294 ******************************************************************************/
295unsigned int gicv2_acknowledge_interrupt(void)
296{
297 assert(driver_data);
298 assert(driver_data->gicc_base);
299
300 return gicc_read_IAR(driver_data->gicc_base);
301}
302
303/*******************************************************************************
304 * This functions writes the GIC cpu interface End Of Interrupt register with
305 * the passed value to finish handling the active secure group 0 interrupt.
306 ******************************************************************************/
307void gicv2_end_of_interrupt(unsigned int id)
308{
309 assert(driver_data);
310 assert(driver_data->gicc_base);
311
312 gicc_write_EOIR(driver_data->gicc_base, id);
313}
314
315/*******************************************************************************
316 * This function returns the type of the interrupt id depending upon the group
317 * this interrupt has been configured under by the interrupt controller i.e.
318 * group0 secure or group1 non secure. It returns zero for Group 0 secure and
319 * one for Group 1 non secure interrupt.
320 ******************************************************************************/
321unsigned int gicv2_get_interrupt_group(unsigned int id)
322{
323 assert(driver_data);
324 assert(driver_data->gicd_base);
325
326 return gicd_get_igroupr(driver_data->gicd_base, id);
327}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100328
329/*******************************************************************************
330 * This function returns the priority of the interrupt the processor is
331 * currently servicing.
332 ******************************************************************************/
333unsigned int gicv2_get_running_priority(void)
334{
335 assert(driver_data);
336 assert(driver_data->gicc_base);
337
338 return gicc_read_rpr(driver_data->gicc_base);
339}
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100340
341/*******************************************************************************
342 * This function sets the GICv2 target mask pattern for the current PE. The PE
343 * target mask is used to translate linear PE index (returned by platform core
344 * position) to a bit mask used when targeting interrupts to a PE, viz. when
345 * raising SGIs and routing SPIs.
346 ******************************************************************************/
347void gicv2_set_pe_target_mask(unsigned int proc_num)
348{
349 assert(driver_data);
350 assert(driver_data->gicd_base);
351 assert(driver_data->target_masks);
352 assert(proc_num < GICV2_MAX_TARGET_PE);
353 assert(proc_num < driver_data->target_masks_num);
354
355 /* Return if the target mask is already populated */
356 if (driver_data->target_masks[proc_num])
357 return;
358
Jeenu Viswambharanfbf5bda2017-11-07 16:10:19 +0000359 /*
360 * Update target register corresponding to this CPU and flush for it to
361 * be visible to other CPUs.
362 */
363 if (driver_data->target_masks[proc_num] == 0) {
364 driver_data->target_masks[proc_num] =
365 gicv2_get_cpuif_id(driver_data->gicd_base);
366#if !HW_ASSISTED_COHERENCY
367 /*
368 * PEs only update their own masks. Primary updates it with
369 * caches on. But because secondaries does it with caches off,
370 * all updates go to memory directly, and there's no danger of
371 * secondaries overwriting each others' mask, despite
372 * target_masks[] not being cache line aligned.
373 */
374 flush_dcache_range((uintptr_t)
375 &driver_data->target_masks[proc_num],
376 sizeof(driver_data->target_masks[proc_num]));
377#endif
378 }
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100379}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100380
381/*******************************************************************************
382 * This function returns the active status of the interrupt (either because the
383 * state is active, or active and pending).
384 ******************************************************************************/
385unsigned int gicv2_get_interrupt_active(unsigned int id)
386{
387 assert(driver_data);
388 assert(driver_data->gicd_base);
389 assert(id <= MAX_SPI_ID);
390
391 return gicd_get_isactiver(driver_data->gicd_base, id);
392}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100393
394/*******************************************************************************
395 * This function enables the interrupt identified by id.
396 ******************************************************************************/
397void gicv2_enable_interrupt(unsigned int id)
398{
399 assert(driver_data);
400 assert(driver_data->gicd_base);
401 assert(id <= MAX_SPI_ID);
402
403 /*
404 * Ensure that any shared variable updates depending on out of band
405 * interrupt trigger are observed before enabling interrupt.
406 */
407 dsbishst();
408 gicd_set_isenabler(driver_data->gicd_base, id);
409}
410
411/*******************************************************************************
412 * This function disables the interrupt identified by id.
413 ******************************************************************************/
414void gicv2_disable_interrupt(unsigned int id)
415{
416 assert(driver_data);
417 assert(driver_data->gicd_base);
418 assert(id <= MAX_SPI_ID);
419
420 /*
421 * Disable interrupt, and ensure that any shared variable updates
422 * depending on out of band interrupt trigger are observed afterwards.
423 */
424 gicd_set_icenabler(driver_data->gicd_base, id);
425 dsbishst();
426}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100427
428/*******************************************************************************
429 * This function sets the interrupt priority as supplied for the given interrupt
430 * id.
431 ******************************************************************************/
432void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
433{
434 assert(driver_data);
435 assert(driver_data->gicd_base);
436 assert(id <= MAX_SPI_ID);
437
438 gicd_set_ipriorityr(driver_data->gicd_base, id, priority);
439}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100440
441/*******************************************************************************
442 * This function assigns group for the interrupt identified by id. The group can
443 * be any of GICV2_INTR_GROUP*
444 ******************************************************************************/
445void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
446{
447 assert(driver_data);
448 assert(driver_data->gicd_base);
449 assert(id <= MAX_SPI_ID);
450
451 /* Serialize read-modify-write to Distributor registers */
452 spin_lock(&gic_lock);
453 switch (type) {
454 case GICV2_INTR_GROUP1:
455 gicd_set_igroupr(driver_data->gicd_base, id);
456 break;
457 case GICV2_INTR_GROUP0:
458 gicd_clr_igroupr(driver_data->gicd_base, id);
459 break;
460 default:
461 assert(0);
462 }
463 spin_unlock(&gic_lock);
464}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100465
466/*******************************************************************************
467 * This function raises the specified SGI to requested targets.
468 *
469 * The proc_num parameter must be the linear index of the target PE in the
470 * system.
471 ******************************************************************************/
472void gicv2_raise_sgi(int sgi_num, int proc_num)
473{
474 unsigned int sgir_val, target;
475
476 assert(driver_data);
477 assert(proc_num < GICV2_MAX_TARGET_PE);
478 assert(driver_data->gicd_base);
479
480 /*
481 * Target masks array must have been supplied, and the core position
482 * should be valid.
483 */
484 assert(driver_data->target_masks);
485 assert(proc_num < driver_data->target_masks_num);
486
487 /* Don't raise SGI if the mask hasn't been populated */
488 target = driver_data->target_masks[proc_num];
489 assert(target != 0);
490
491 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num);
492
493 /*
494 * Ensure that any shared variable updates depending on out of band
495 * interrupt trigger are observed before raising SGI.
496 */
497 dsbishst();
498 gicd_write_sgir(driver_data->gicd_base, sgir_val);
499}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100500
501/*******************************************************************************
502 * This function sets the interrupt routing for the given SPI interrupt id.
503 * The interrupt routing is specified in routing mode. The proc_num parameter is
504 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target
505 * all PEs.
506 ******************************************************************************/
507void gicv2_set_spi_routing(unsigned int id, int proc_num)
508{
509 int target;
510
511 assert(driver_data);
512 assert(driver_data->gicd_base);
513
514 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
515
516 /*
517 * Target masks array must have been supplied, and the core position
518 * should be valid.
519 */
520 assert(driver_data->target_masks);
521 assert(proc_num < GICV2_MAX_TARGET_PE);
522 assert(proc_num < driver_data->target_masks_num);
523
524 if (proc_num < 0) {
525 /* Target all PEs */
526 target = GIC_TARGET_CPU_MASK;
527 } else {
528 /* Don't route interrupt if the mask hasn't been populated */
529 target = driver_data->target_masks[proc_num];
530 assert(target != 0);
531 }
532
533 gicd_set_itargetsr(driver_data->gicd_base, id, target);
534}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100535
536/*******************************************************************************
537 * This function clears the pending status of an interrupt identified by id.
538 ******************************************************************************/
539void gicv2_clear_interrupt_pending(unsigned int id)
540{
541 assert(driver_data);
542 assert(driver_data->gicd_base);
543
544 /* SGIs can't be cleared pending */
545 assert(id >= MIN_PPI_ID);
546
547 /*
548 * Clear pending interrupt, and ensure that any shared variable updates
549 * depending on out of band interrupt trigger are observed afterwards.
550 */
551 gicd_set_icpendr(driver_data->gicd_base, id);
552 dsbishst();
553}
554
555/*******************************************************************************
556 * This function sets the pending status of an interrupt identified by id.
557 ******************************************************************************/
558void gicv2_set_interrupt_pending(unsigned int id)
559{
560 assert(driver_data);
561 assert(driver_data->gicd_base);
562
563 /* SGIs can't be cleared pending */
564 assert(id >= MIN_PPI_ID);
565
566 /*
567 * Ensure that any shared variable updates depending on out of band
568 * interrupt trigger are observed before setting interrupt pending.
569 */
570 dsbishst();
571 gicd_set_ispendr(driver_data->gicd_base, id);
572}
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100573
574/*******************************************************************************
575 * This function sets the PMR register with the supplied value. Returns the
576 * original PMR.
577 ******************************************************************************/
578unsigned int gicv2_set_pmr(unsigned int mask)
579{
580 unsigned int old_mask;
581
582 assert(driver_data);
583 assert(driver_data->gicc_base);
584
585 old_mask = gicc_read_pmr(driver_data->gicc_base);
586
587 /*
588 * Order memory updates w.r.t. PMR write, and ensure they're visible
589 * before potential out of band interrupt trigger because of PMR update.
590 */
591 dmbishst();
592 gicc_write_pmr(driver_data->gicc_base, mask);
593 dsbishst();
594
595 return old_mask;
596}