blob: 6d813774d2bb291ab09e0009610db33db98cdaea [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Zelalem91d80612020-02-12 10:37:03 -06002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <string.h>
9
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/bl_common.h>
13#include <common/debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Sandeep Tripathy12030042020-08-17 20:22:13 +053015#include <drivers/delay_timer.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <lib/el3_runtime/context_mgmt.h>
17#include <lib/utils.h>
18#include <plat/common/platform.h>
19
Dan Handley714a0d22014-04-09 13:13:04 +010020#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010021
Achin Gupta607084e2014-02-09 18:24:19 +000022/*
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000023 * SPD power management operations, expected to be supplied by the registered
24 * SPD on successful SP initialization
Achin Gupta607084e2014-02-09 18:24:19 +000025 */
Dan Handleye2712bc2014-04-10 15:37:22 +010026const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +000027
Soby Mathew981487a2015-07-13 14:10:57 +010028/*
29 * PSCI requested local power state map. This array is used to store the local
30 * power states requested by a CPU for power levels from level 1 to
31 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power
32 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
33 * CPU are the same.
34 *
35 * During state coordination, the platform is passed an array containing the
36 * local states requested for a particular non cpu power domain by each cpu
37 * within the domain.
38 *
39 * TODO: Dense packing of the requested states will cause cache thrashing
40 * when multiple power domains write to it. If we allocate the requested
41 * states at each power level in a cache-line aligned per-domain memory,
42 * the cache thrashing can be avoided.
43 */
44static plat_local_state_t
45 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
46
Pankaj Gupta02c35682019-10-15 15:44:45 +053047unsigned int psci_plat_core_count;
Soby Mathew981487a2015-07-13 14:10:57 +010048
Achin Gupta4f6ad662013-10-25 09:08:21 +010049/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010050 * Arrays that hold the platform's power domain tree information for state
51 * management of power domains.
52 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
53 * which is an ancestor of a CPU power domain.
54 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
Achin Gupta4f6ad662013-10-25 09:08:21 +010055 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010056non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
Soby Mathew2ae20432015-01-08 18:02:44 +000057#if USE_COHERENT_MEM
Soren Brinkmann46dd1702016-01-14 10:11:05 -080058__section("tzfw_coherent_mem")
Soby Mathew2ae20432015-01-08 18:02:44 +000059#endif
60;
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +000062/* Lock for PSCI state coordination */
63DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +010064
Soby Mathew981487a2015-07-13 14:10:57 +010065cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
66
Achin Gupta4f6ad662013-10-25 09:08:21 +010067/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010068 * Pointer to functions exported by the platform to complete power mgmt. ops
69 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010070const plat_psci_ops_t *psci_plat_pm_ops;
Achin Gupta4f6ad662013-10-25 09:08:21 +010071
Soby Mathew981487a2015-07-13 14:10:57 +010072/******************************************************************************
73 * Check that the maximum power level supported by the platform makes sense
74 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010075CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
76 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
77 assert_platform_max_pwrlvl_check);
Soby Mathew2b7de2b2015-02-12 14:45:02 +000078
Soby Mathew981487a2015-07-13 14:10:57 +010079/*
80 * The plat_local_state used by the platform is one of these types: RUN,
81 * RETENTION and OFF. The platform can define further sub-states for each type
82 * apart from RUN. This categorization is done to verify the sanity of the
83 * psci_power_state passed by the platform and to print debug information. The
84 * categorization is done on the basis of the following conditions:
85 *
86 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN.
87 *
88 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is
89 * STATE_TYPE_RETN.
90 *
91 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is
92 * STATE_TYPE_OFF.
93 */
94typedef enum plat_local_state_type {
95 STATE_TYPE_RUN = 0,
96 STATE_TYPE_RETN,
97 STATE_TYPE_OFF
98} plat_local_state_type_t;
99
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100100/* Function used to categorize plat_local_state. */
101static plat_local_state_type_t find_local_state_type(plat_local_state_t state)
102{
103 if (state != 0U) {
104 if (state > PLAT_MAX_RET_STATE) {
105 return STATE_TYPE_OFF;
106 } else {
107 return STATE_TYPE_RETN;
108 }
109 } else {
110 return STATE_TYPE_RUN;
111 }
112}
Soby Mathew981487a2015-07-13 14:10:57 +0100113
114/******************************************************************************
115 * Check that the maximum retention level supported by the platform is less
116 * than the maximum off level.
117 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100118CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE,
Soby Mathew981487a2015-07-13 14:10:57 +0100119 assert_platform_max_off_and_retn_state_check);
120
121/******************************************************************************
122 * This function ensures that the power state parameter in a CPU_SUSPEND request
123 * is valid. If so, it returns the requested states for each power level.
124 *****************************************************************************/
125int psci_validate_power_state(unsigned int power_state,
126 psci_power_state_t *state_info)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100127{
Soby Mathew981487a2015-07-13 14:10:57 +0100128 /* Check SBZ bits in power state are zero */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100129 if (psci_check_power_state(power_state) != 0U)
Soby Mathew981487a2015-07-13 14:10:57 +0100130 return PSCI_E_INVALID_PARAMS;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100131
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100132 assert(psci_plat_pm_ops->validate_power_state != NULL);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100133
Soby Mathew981487a2015-07-13 14:10:57 +0100134 /* Validate the power_state using platform pm_ops */
135 return psci_plat_pm_ops->validate_power_state(power_state, state_info);
136}
Achin Guptaf6b9e992014-07-31 11:19:11 +0100137
Soby Mathew981487a2015-07-13 14:10:57 +0100138/******************************************************************************
139 * This function retrieves the `psci_power_state_t` for system suspend from
140 * the platform.
141 *****************************************************************************/
142void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
143{
144 /*
145 * Assert that the required pm_ops hook is implemented to ensure that
146 * the capability detected during psci_setup() is valid.
147 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100148 assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL);
Soby Mathew981487a2015-07-13 14:10:57 +0100149
150 /*
151 * Query the platform for the power_state required for system suspend
152 */
153 psci_plat_pm_ops->get_sys_suspend_power_state(state_info);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100154}
155
156/*******************************************************************************
Soby Mathew96168382014-12-17 14:47:57 +0000157 * This function verifies that the all the other cores in the system have been
158 * turned OFF and the current CPU is the last running CPU in the system.
159 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
160 * otherwise.
161 ******************************************************************************/
162unsigned int psci_is_last_on_cpu(void)
163{
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300164 unsigned int cpu_idx, my_idx = plat_my_core_pos();
Soby Mathew96168382014-12-17 14:47:57 +0000165
Pankaj Gupta02c35682019-10-15 15:44:45 +0530166 for (cpu_idx = 0; cpu_idx < psci_plat_core_count;
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300167 cpu_idx++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100168 if (cpu_idx == my_idx) {
169 assert(psci_get_aff_info_state() == AFF_STATE_ON);
Soby Mathew96168382014-12-17 14:47:57 +0000170 continue;
171 }
172
Soby Mathew981487a2015-07-13 14:10:57 +0100173 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
Soby Mathew96168382014-12-17 14:47:57 +0000174 return 0;
175 }
176
177 return 1;
178}
179
180/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100181 * Routine to return the maximum power level to traverse to after a cpu has
182 * been physically powered up. It is expected to be called immediately after
183 * reset from assembler code.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100184 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100185static unsigned int get_power_on_target_pwrlvl(void)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100186{
Soby Mathew011ca182015-07-29 17:05:03 +0100187 unsigned int pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100188
189 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100190 * Assume that this cpu was suspended and retrieve its target power
191 * level. If it is invalid then it could only have been turned off
192 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a
193 * cpu can be turned off to.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100194 */
Soby Mathew981487a2015-07-13 14:10:57 +0100195 pwrlvl = psci_get_suspend_pwrlvl();
Soby Mathew011ca182015-07-29 17:05:03 +0100196 if (pwrlvl == PSCI_INVALID_PWR_LVL)
Soby Mathew981487a2015-07-13 14:10:57 +0100197 pwrlvl = PLAT_MAX_PWR_LVL;
Deepika Bhavnani523024c2019-08-17 01:10:02 +0300198 assert(pwrlvl < PSCI_INVALID_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100199 return pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100200}
201
Soby Mathew981487a2015-07-13 14:10:57 +0100202/******************************************************************************
203 * Helper function to update the requested local power state array. This array
204 * does not store the requested state for the CPU power level. Hence an
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300205 * assertion is added to prevent us from accessing the CPU power level.
Soby Mathew981487a2015-07-13 14:10:57 +0100206 *****************************************************************************/
207static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
208 unsigned int cpu_idx,
209 plat_local_state_t req_pwr_state)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100210{
Soby Mathew981487a2015-07-13 14:10:57 +0100211 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300212 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
Pankaj Gupta02c35682019-10-15 15:44:45 +0530213 (cpu_idx < psci_plat_core_count)) {
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300214 psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
215 }
Achin Guptaf6b9e992014-07-31 11:19:11 +0100216}
217
Soby Mathew981487a2015-07-13 14:10:57 +0100218/******************************************************************************
219 * This function initializes the psci_req_local_pwr_states.
220 *****************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +0100221void __init psci_init_req_local_pwr_states(void)
Achin Guptaa45e3972013-12-05 15:10:48 +0000222{
Soby Mathew981487a2015-07-13 14:10:57 +0100223 /* Initialize the requested state of all non CPU power domains as OFF */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100224 unsigned int pwrlvl;
Pankaj Gupta02c35682019-10-15 15:44:45 +0530225 unsigned int core;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100226
227 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
Pankaj Gupta02c35682019-10-15 15:44:45 +0530228 for (core = 0; core < psci_plat_core_count; core++) {
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100229 psci_req_local_pwr_states[pwrlvl][core] =
230 PLAT_MAX_OFF_STATE;
231 }
232 }
Soby Mathew981487a2015-07-13 14:10:57 +0100233}
Achin Guptaa45e3972013-12-05 15:10:48 +0000234
Soby Mathew981487a2015-07-13 14:10:57 +0100235/******************************************************************************
236 * Helper function to return a reference to an array containing the local power
237 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the
238 * array will be the number of cpu power domains of which this power domain is
239 * an ancestor. These requested states will be used to determine a suitable
240 * target state for this power domain during psci state coordination. An
241 * assertion is added to prevent us from accessing the CPU power level.
242 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100243static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300244 unsigned int cpu_idx)
Soby Mathew981487a2015-07-13 14:10:57 +0100245{
246 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100247
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300248 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
Pankaj Gupta02c35682019-10-15 15:44:45 +0530249 (cpu_idx < psci_plat_core_count)) {
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300250 return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
251 } else
252 return NULL;
Soby Mathew981487a2015-07-13 14:10:57 +0100253}
Achin Guptaa45e3972013-12-05 15:10:48 +0000254
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000255/*
256 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent
257 * memory.
258 *
259 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory,
260 * it's accessed by both cached and non-cached participants. To serve the common
261 * minimum, perform a cache flush before read and after write so that non-cached
262 * participants operate on latest data in main memory.
263 *
264 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent
265 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent.
266 * In both cases, no cache operations are required.
267 */
268
269/*
270 * Retrieve local state of non-CPU power domain node from a non-cached CPU,
271 * after any required cache maintenance operation.
272 */
273static plat_local_state_t get_non_cpu_pd_node_local_state(
274 unsigned int parent_idx)
275{
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500276#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000277 flush_dcache_range(
278 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
279 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
280#endif
281 return psci_non_cpu_pd_nodes[parent_idx].local_state;
282}
283
284/*
285 * Update local state of non-CPU power domain node from a cached CPU; perform
286 * any required cache maintenance operation afterwards.
287 */
288static void set_non_cpu_pd_node_local_state(unsigned int parent_idx,
289 plat_local_state_t state)
290{
291 psci_non_cpu_pd_nodes[parent_idx].local_state = state;
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500292#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000293 flush_dcache_range(
294 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
295 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
296#endif
297}
298
Soby Mathew981487a2015-07-13 14:10:57 +0100299/******************************************************************************
300 * Helper function to return the current local power state of each power domain
301 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This
302 * function will be called after a cpu is powered on to find the local state
303 * each power domain has emerged from.
304 *****************************************************************************/
Achin Gupta9b2bf252016-06-28 16:46:15 +0100305void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
306 psci_power_state_t *target_state)
Soby Mathew981487a2015-07-13 14:10:57 +0100307{
Soby Mathew011ca182015-07-29 17:05:03 +0100308 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100309 plat_local_state_t *pd_state = target_state->pwr_domain_state;
310
311 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state();
312 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
313
314 /* Copy the local power state from node to state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100315 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000316 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx);
Soby Mathew981487a2015-07-13 14:10:57 +0100317 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
318 }
319
320 /* Set the the higher levels to RUN */
321 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
322 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
323}
324
325/******************************************************************************
326 * Helper function to set the target local power state that each power domain
327 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will
328 * enter. This function will be called after coordination of requested power
329 * states has been done for each power level.
330 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100331static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100332 const psci_power_state_t *target_state)
333{
Soby Mathew011ca182015-07-29 17:05:03 +0100334 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100335 const plat_local_state_t *pd_state = target_state->pwr_domain_state;
336
337 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]);
Achin Guptaa45e3972013-12-05 15:10:48 +0000338
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100339 /*
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000340 * Need to flush as local_state might be accessed with Data Cache
Soby Mathew981487a2015-07-13 14:10:57 +0100341 * disabled during power on
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100342 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000343 psci_flush_cpu_data(psci_svc_cpu_data.local_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100344
345 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
346
347 /* Copy the local_state from state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100348 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000349 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]);
Soby Mathew981487a2015-07-13 14:10:57 +0100350 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
351 }
Achin Guptaa45e3972013-12-05 15:10:48 +0000352}
353
Soby Mathew981487a2015-07-13 14:10:57 +0100354
Achin Guptaa45e3972013-12-05 15:10:48 +0000355/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100356 * PSCI helper function to get the parent nodes corresponding to a cpu_index.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100357 ******************************************************************************/
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300358void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100359 unsigned int end_lvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100360 unsigned int *node_index)
Soby Mathew981487a2015-07-13 14:10:57 +0100361{
362 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
Varun Wadekar66231d12017-06-07 09:57:42 -0700363 unsigned int i;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100364 unsigned int *node = node_index;
Soby Mathew981487a2015-07-13 14:10:57 +0100365
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100366 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) {
367 *node = parent_node;
368 node++;
Soby Mathew981487a2015-07-13 14:10:57 +0100369 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
370 }
371}
372
373/******************************************************************************
374 * This function is invoked post CPU power up and initialization. It sets the
375 * affinity info state, target power state and requested power state for the
376 * current CPU and all its ancestor power domains to RUN.
377 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100378void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl)
Soby Mathew981487a2015-07-13 14:10:57 +0100379{
Soby Mathew011ca182015-07-29 17:05:03 +0100380 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100381 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
382
383 /* Reset the local_state to RUN for the non cpu power domains. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100384 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000385 set_non_cpu_pd_node_local_state(parent_idx,
386 PSCI_LOCAL_STATE_RUN);
Soby Mathew981487a2015-07-13 14:10:57 +0100387 psci_set_req_local_pwr_state(lvl,
388 cpu_idx,
389 PSCI_LOCAL_STATE_RUN);
390 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
391 }
392
393 /* Set the affinity info state to ON */
394 psci_set_aff_info_state(AFF_STATE_ON);
395
396 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000397 psci_flush_cpu_data(psci_svc_cpu_data);
Soby Mathew981487a2015-07-13 14:10:57 +0100398}
399
400/******************************************************************************
401 * This function is passed the local power states requested for each power
402 * domain (state_info) between the current CPU domain and its ancestors until
403 * the target power level (end_pwrlvl). It updates the array of requested power
404 * states with this information.
405 *
406 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
407 * retrieves the states requested by all the cpus of which the power domain at
408 * that level is an ancestor. It passes this information to the platform to
409 * coordinate and return the target power state. If the target state for a level
410 * is RUN then subsequent levels are not considered. At the CPU level, state
411 * coordination is not required. Hence, the requested and the target states are
412 * the same.
413 *
414 * The 'state_info' is updated with the target state for each level between the
415 * CPU and the 'end_pwrlvl' and returned to the caller.
416 *
417 * This function will only be invoked with data cache enabled and while
418 * powering down a core.
419 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100420void psci_do_state_coordination(unsigned int end_pwrlvl,
421 psci_power_state_t *state_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100422{
Soby Mathew981487a2015-07-13 14:10:57 +0100423 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300424 unsigned int start_idx;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100425 unsigned int ncpus;
Soby Mathew981487a2015-07-13 14:10:57 +0100426 plat_local_state_t target_state, *req_states;
427
Soby Mathew1298e692016-02-02 14:23:10 +0000428 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100429 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
430
431 /* For level 0, the requested state will be equivalent
432 to target state */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100433 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100434
435 /* First update the requested power state */
436 psci_set_req_local_pwr_state(lvl, cpu_idx,
437 state_info->pwr_domain_state[lvl]);
438
439 /* Get the requested power states for this power level */
440 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
441 req_states = psci_get_req_local_pwr_states(lvl, start_idx);
442
443 /*
444 * Let the platform coordinate amongst the requested states at
445 * this power level and return the target local power state.
446 */
447 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus;
448 target_state = plat_get_target_pwr_state(lvl,
449 req_states,
450 ncpus);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100451
Soby Mathew981487a2015-07-13 14:10:57 +0100452 state_info->pwr_domain_state[lvl] = target_state;
453
454 /* Break early if the negotiated target power state is RUN */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100455 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
Soby Mathew981487a2015-07-13 14:10:57 +0100456 break;
457
458 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
459 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100460
461 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100462 * This is for cases when we break out of the above loop early because
463 * the target power state is RUN at a power level < end_pwlvl.
464 * We update the requested power state from state_info and then
465 * set the target state as RUN.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100466 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100467 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100468 psci_set_req_local_pwr_state(lvl, cpu_idx,
469 state_info->pwr_domain_state[lvl]);
470 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100471
Soby Mathew981487a2015-07-13 14:10:57 +0100472 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100473
Soby Mathew981487a2015-07-13 14:10:57 +0100474 /* Update the target state in the power domain nodes */
475 psci_set_target_local_pwr_states(end_pwrlvl, state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100476}
477
Soby Mathew981487a2015-07-13 14:10:57 +0100478/******************************************************************************
479 * This function validates a suspend request by making sure that if a standby
480 * state is requested then no power level is turned off and the highest power
481 * level is placed in a standby/retention state.
482 *
483 * It also ensures that the state level X will enter is not shallower than the
484 * state level X + 1 will enter.
485 *
486 * This validation will be enabled only for DEBUG builds as the platform is
487 * expected to perform these validations as well.
488 *****************************************************************************/
489int psci_validate_suspend_req(const psci_power_state_t *state_info,
490 unsigned int is_power_down_state)
Achin Gupta0959db52013-12-02 17:33:04 +0000491{
Soby Mathew981487a2015-07-13 14:10:57 +0100492 unsigned int max_off_lvl, target_lvl, max_retn_lvl;
493 plat_local_state_t state;
494 plat_local_state_type_t req_state_type, deepest_state_type;
495 int i;
Achin Gupta0959db52013-12-02 17:33:04 +0000496
Soby Mathew981487a2015-07-13 14:10:57 +0100497 /* Find the target suspend power level */
498 target_lvl = psci_find_target_suspend_lvl(state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100499 if (target_lvl == PSCI_INVALID_PWR_LVL)
Achin Gupta0959db52013-12-02 17:33:04 +0000500 return PSCI_E_INVALID_PARAMS;
501
Soby Mathew981487a2015-07-13 14:10:57 +0100502 /* All power domain levels are in a RUN state to begin with */
503 deepest_state_type = STATE_TYPE_RUN;
504
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100505 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) {
Soby Mathew981487a2015-07-13 14:10:57 +0100506 state = state_info->pwr_domain_state[i];
507 req_state_type = find_local_state_type(state);
508
509 /*
510 * While traversing from the highest power level to the lowest,
511 * the state requested for lower levels has to be the same or
512 * deeper i.e. equal to or greater than the state at the higher
513 * levels. If this condition is true, then the requested state
514 * becomes the deepest state encountered so far.
515 */
516 if (req_state_type < deepest_state_type)
517 return PSCI_E_INVALID_PARAMS;
518 deepest_state_type = req_state_type;
519 }
520
521 /* Find the highest off power level */
522 max_off_lvl = psci_find_max_off_lvl(state_info);
523
524 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */
Soby Mathew011ca182015-07-29 17:05:03 +0100525 max_retn_lvl = PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100526 if (target_lvl != max_off_lvl)
527 max_retn_lvl = target_lvl;
528
529 /*
530 * If this is not a request for a power down state then max off level
531 * has to be invalid and max retention level has to be a valid power
532 * level.
533 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100534 if ((is_power_down_state == 0U) &&
535 ((max_off_lvl != PSCI_INVALID_PWR_LVL) ||
536 (max_retn_lvl == PSCI_INVALID_PWR_LVL)))
Achin Gupta0959db52013-12-02 17:33:04 +0000537 return PSCI_E_INVALID_PARAMS;
538
539 return PSCI_E_SUCCESS;
540}
541
Soby Mathew981487a2015-07-13 14:10:57 +0100542/******************************************************************************
543 * This function finds the highest power level which will be powered down
544 * amongst all the power levels specified in the 'state_info' structure
545 *****************************************************************************/
546unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
Achin Guptacab78e42014-07-28 00:09:01 +0100547{
Soby Mathew981487a2015-07-13 14:10:57 +0100548 int i;
Achin Guptacab78e42014-07-28 00:09:01 +0100549
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100550 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
551 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0)
552 return (unsigned int) i;
Soby Mathew981487a2015-07-13 14:10:57 +0100553 }
554
Soby Mathew011ca182015-07-29 17:05:03 +0100555 return PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100556}
557
558/******************************************************************************
559 * This functions finds the level of the highest power domain which will be
560 * placed in a low power state during a suspend operation.
561 *****************************************************************************/
562unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info)
563{
564 int i;
565
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100566 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
567 if (is_local_state_run(state_info->pwr_domain_state[i]) == 0)
568 return (unsigned int) i;
Achin Guptacab78e42014-07-28 00:09:01 +0100569 }
Soby Mathew981487a2015-07-13 14:10:57 +0100570
Soby Mathew011ca182015-07-29 17:05:03 +0100571 return PSCI_INVALID_PWR_LVL;
Achin Guptacab78e42014-07-28 00:09:01 +0100572}
573
574/*******************************************************************************
Andrew F. Davis74e89782019-06-04 10:46:54 -0400575 * This function is passed the highest level in the topology tree that the
576 * operation should be applied to and a list of node indexes. It picks up locks
577 * from the node index list in order of increasing power domain level in the
578 * range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000579 ******************************************************************************/
Andrew F. Davis74e89782019-06-04 10:46:54 -0400580void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
581 const unsigned int *parent_nodes)
Achin Gupta0959db52013-12-02 17:33:04 +0000582{
Andrew F. Davis74e89782019-06-04 10:46:54 -0400583 unsigned int parent_idx;
Soby Mathew011ca182015-07-29 17:05:03 +0100584 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000585
Soby Mathew981487a2015-07-13 14:10:57 +0100586 /* No locking required for level 0. Hence start locking from level 1 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100587 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
Andrew F. Davis74e89782019-06-04 10:46:54 -0400588 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100589 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000590 }
591}
592
593/*******************************************************************************
Andrew F. Davis74e89782019-06-04 10:46:54 -0400594 * This function is passed the highest level in the topology tree that the
595 * operation should be applied to and a list of node indexes. It releases the
596 * locks in order of decreasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000597 ******************************************************************************/
Andrew F. Davis74e89782019-06-04 10:46:54 -0400598void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
599 const unsigned int *parent_nodes)
Achin Gupta0959db52013-12-02 17:33:04 +0000600{
Andrew F. Davis74e89782019-06-04 10:46:54 -0400601 unsigned int parent_idx;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100602 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000603
Soby Mathew981487a2015-07-13 14:10:57 +0100604 /* Unlock top down. No unlocking required for level 0. */
Zelalem91d80612020-02-12 10:37:03 -0600605 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) {
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100606 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100607 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000608 }
609}
610
611/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100612 * Simple routine to determine whether a mpidr is valid or not.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100613 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100614int psci_validate_mpidr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100615{
Soby Mathew981487a2015-07-13 14:10:57 +0100616 if (plat_core_pos_by_mpidr(mpidr) < 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100617 return PSCI_E_INVALID_PARAMS;
Soby Mathew981487a2015-07-13 14:10:57 +0100618
619 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100620}
621
622/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100623 * This function determines the full entrypoint information for the requested
Soby Mathew8595b872015-01-06 15:36:38 +0000624 * PSCI entrypoint on power on/resume and returns it.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100625 ******************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700626#ifdef __aarch64__
Soby Mathewf1f97a12015-07-15 12:13:26 +0100627static int psci_get_ns_ep_info(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100628 uintptr_t entrypoint,
629 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100630{
Soby Mathewa0fedc42016-06-16 14:52:04 +0100631 u_register_t ep_attr, sctlr;
Soby Mathew011ca182015-07-29 17:05:03 +0100632 unsigned int daif, ee, mode;
Soby Mathewa0fedc42016-06-16 14:52:04 +0100633 u_register_t ns_scr_el3 = read_scr_el3();
634 u_register_t ns_sctlr_el1 = read_sctlr_el1();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100635
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100636 sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
637 read_sctlr_el2() : ns_sctlr_el1;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100638 ee = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100639
Andrew Thoelke4e126072014-06-04 21:10:52 +0100640 ep_attr = NON_SECURE | EP_ST_DISABLE;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100641 if ((sctlr & SCTLR_EE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100642 ep_attr |= EP_EE_BIG;
643 ee = 1;
644 }
Soby Mathew8595b872015-01-06 15:36:38 +0000645 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100646
Soby Mathew8595b872015-01-06 15:36:38 +0000647 ep->pc = entrypoint;
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000648 zeromem(&ep->args, sizeof(ep->args));
Soby Mathew8595b872015-01-06 15:36:38 +0000649 ep->args.arg0 = context_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100650
651 /*
652 * Figure out whether the cpu enters the non-secure address space
653 * in aarch32 or aarch64
654 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100655 if ((ns_scr_el3 & SCR_RW_BIT) != 0U) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100656
657 /*
658 * Check whether a Thumb entry point has been provided for an
659 * aarch64 EL
660 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100661 if ((entrypoint & 0x1UL) != 0UL)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100662 return PSCI_E_INVALID_ADDRESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100663
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100664 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100665
Soby Mathew8595b872015-01-06 15:36:38 +0000666 ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100667 } else {
668
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100669 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
670 MODE32_hyp : MODE32_svc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100671
672 /*
673 * TODO: Choose async. exception bits if HYP mode is not
674 * implemented according to the values of SCR.{AW, FW} bits
675 */
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100676 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
677
Soby Mathew8595b872015-01-06 15:36:38 +0000678 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100679 }
680
Andrew Thoelke4e126072014-06-04 21:10:52 +0100681 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100682}
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700683#else /* !__aarch64__ */
684static int psci_get_ns_ep_info(entry_point_info_t *ep,
685 uintptr_t entrypoint,
686 u_register_t context_id)
687{
688 u_register_t ep_attr;
689 unsigned int aif, ee, mode;
690 u_register_t scr = read_scr();
691 u_register_t ns_sctlr, sctlr;
692
693 /* Switch to non secure state */
694 write_scr(scr | SCR_NS_BIT);
695 isb();
696 ns_sctlr = read_sctlr();
697
698 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
699
700 /* Return to original state */
701 write_scr(scr);
702 isb();
703 ee = 0;
704
705 ep_attr = NON_SECURE | EP_ST_DISABLE;
706 if (sctlr & SCTLR_EE_BIT) {
707 ep_attr |= EP_EE_BIG;
708 ee = 1;
709 }
710 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
711
712 ep->pc = entrypoint;
713 zeromem(&ep->args, sizeof(ep->args));
714 ep->args.arg0 = context_id;
715
716 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
717
718 /*
719 * TODO: Choose async. exception bits if HYP mode is not
720 * implemented according to the values of SCR.{AW, FW} bits
721 */
722 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
723
724 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
725
726 return PSCI_E_SUCCESS;
727}
728
729#endif /* __aarch64__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100730
731/*******************************************************************************
Soby Mathewf1f97a12015-07-15 12:13:26 +0100732 * This function validates the entrypoint with the platform layer if the
733 * appropriate pm_ops hook is exported by the platform and returns the
734 * 'entry_point_info'.
735 ******************************************************************************/
736int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100737 uintptr_t entrypoint,
738 u_register_t context_id)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100739{
740 int rc;
741
742 /* Validate the entrypoint using platform psci_ops */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100743 if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100744 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
745 if (rc != PSCI_E_SUCCESS)
746 return PSCI_E_INVALID_ADDRESS;
747 }
748
749 /*
750 * Verify and derive the re-entry information for
751 * the non-secure world from the non-secure state from
752 * where this call originated.
753 */
754 rc = psci_get_ns_ep_info(ep, entrypoint, context_id);
755 return rc;
756}
757
758/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100759 * Generic handler which is called when a cpu is physically powered on. It
Soby Mathew981487a2015-07-13 14:10:57 +0100760 * traverses the node information and finds the highest power level powered
761 * off and performs generic, architectural, platform setup and state management
762 * to power on that power level and power levels below it.
763 * e.g. For a cpu that's been powered on, it will call the platform specific
764 * code to enable the gic cpu interface and for a cluster it will enable
765 * coherency at the interconnect level in addition to gic cpu interface.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100766 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100767void psci_warmboot_entrypoint(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100768{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100769 unsigned int end_pwrlvl;
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300770 unsigned int cpu_idx = plat_my_core_pos();
Andrew F. Davis74e89782019-06-04 10:46:54 -0400771 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
Soby Mathew981487a2015-07-13 14:10:57 +0100772 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100773
Achin Gupta4f6ad662013-10-25 09:08:21 +0100774 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100775 * Verify that we have been explicitly turned ON or resumed from
776 * suspend.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100777 */
Soby Mathew981487a2015-07-13 14:10:57 +0100778 if (psci_get_aff_info_state() == AFF_STATE_OFF) {
Andrew Walbran8fe72b92020-01-23 16:22:44 +0000779 ERROR("Unexpected affinity info state.\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000780 panic();
Soby Mathew981487a2015-07-13 14:10:57 +0100781 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100782
783 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100784 * Get the maximum power domain level to traverse to after this cpu
785 * has been physically powered up.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100786 */
Soby Mathew981487a2015-07-13 14:10:57 +0100787 end_pwrlvl = get_power_on_target_pwrlvl();
Achin Guptaf6b9e992014-07-31 11:19:11 +0100788
Andrew F. Davis74e89782019-06-04 10:46:54 -0400789 /* Get the parent nodes */
790 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
791
Achin Guptaf6b9e992014-07-31 11:19:11 +0100792 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100793 * This function acquires the lock corresponding to each power level so
794 * that by the time all locks are taken, the system topology is snapshot
795 * and state management can be done safely.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100796 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400797 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100798
Soby Mathew8336f682017-10-16 15:19:31 +0100799 psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
800
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100801#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000802 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100803#endif
804
Achin Gupta4f6ad662013-10-25 09:08:21 +0100805 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100806 * This CPU could be resuming from suspend or it could have just been
807 * turned on. To distinguish between these 2 cases, we examine the
808 * affinity state of the CPU:
809 * - If the affinity state is ON_PENDING then it has just been
810 * turned on.
811 * - Else it is resuming from suspend.
812 *
813 * Depending on the type of warm reset identified, choose the right set
814 * of power management handler and perform the generic, architecture
815 * and platform specific handling.
Achin Guptacab78e42014-07-28 00:09:01 +0100816 */
Soby Mathew981487a2015-07-13 14:10:57 +0100817 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
818 psci_cpu_on_finish(cpu_idx, &state_info);
819 else
820 psci_cpu_suspend_finish(cpu_idx, &state_info);
Achin Guptacab78e42014-07-28 00:09:01 +0100821
822 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100823 * Set the requested and target state of this CPU and all the higher
824 * power domains which are ancestors of this CPU to run.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100825 */
Soby Mathew981487a2015-07-13 14:10:57 +0100826 psci_set_pwr_domains_to_run(end_pwrlvl);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100827
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100828#if ENABLE_PSCI_STAT
829 /*
830 * Update PSCI stats.
831 * Caches are off when writing stats data on the power down path.
832 * Since caches are now enabled, it's necessary to do cache
833 * maintenance before reading that same data.
834 */
dp-arm66abfbe2017-01-31 13:01:04 +0000835 psci_stats_update_pwr_up(end_pwrlvl, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100836#endif
837
Achin Guptaf6b9e992014-07-31 11:19:11 +0100838 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100839 * This loop releases the lock corresponding to each power level
Achin Gupta0959db52013-12-02 17:33:04 +0000840 * in the reverse order to which they were acquired.
841 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400842 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100843}
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000844
845/*******************************************************************************
846 * This function initializes the set of hooks that PSCI invokes as part of power
847 * management operation. The power management hooks are expected to be provided
848 * by the SPD, after it finishes all its initialization
849 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100850void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000851{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100852 assert(pm != NULL);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000853 psci_spd_pm = pm;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000854
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100855 if (pm->svc_migrate != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000856 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
857
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100858 if (pm->svc_migrate_info != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000859 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
860 | define_psci_cap(PSCI_MIG_INFO_TYPE);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000861}
Juan Castillo4dc4a472014-08-12 11:17:06 +0100862
863/*******************************************************************************
Soby Mathew110fe362014-10-23 10:35:34 +0100864 * This function invokes the migrate info hook in the spd_pm_ops. It performs
865 * the necessary return value validation. If the Secure Payload is UP and
866 * migrate capable, it returns the mpidr of the CPU on which the Secure payload
867 * is resident through the mpidr parameter. Else the value of the parameter on
868 * return is undefined.
869 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100870int psci_spd_migrate_info(u_register_t *mpidr)
Soby Mathew110fe362014-10-23 10:35:34 +0100871{
872 int rc;
873
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100874 if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL))
Soby Mathew110fe362014-10-23 10:35:34 +0100875 return PSCI_E_NOT_SUPPORTED;
876
877 rc = psci_spd_pm->svc_migrate_info(mpidr);
878
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100879 assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) ||
880 (rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED));
Soby Mathew110fe362014-10-23 10:35:34 +0100881
882 return rc;
883}
884
885
886/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100887 * This function prints the state of all power domains present in the
Juan Castillo4dc4a472014-08-12 11:17:06 +0100888 * system
889 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100890void psci_print_power_domain_map(void)
Juan Castillo4dc4a472014-08-12 11:17:06 +0100891{
892#if LOG_LEVEL >= LOG_LEVEL_INFO
Pankaj Gupta02c35682019-10-15 15:44:45 +0530893 unsigned int idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100894 plat_local_state_t state;
895 plat_local_state_type_t state_type;
896
Juan Castillo4dc4a472014-08-12 11:17:06 +0100897 /* This array maps to the PSCI_STATE_X definitions in psci.h */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100898 static const char * const psci_state_type_str[] = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100899 "ON",
Soby Mathew981487a2015-07-13 14:10:57 +0100900 "RETENTION",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100901 "OFF",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100902 };
903
Soby Mathew981487a2015-07-13 14:10:57 +0100904 INFO("PSCI Power Domain Map:\n");
Pankaj Gupta02c35682019-10-15 15:44:45 +0530905 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count);
Soby Mathew981487a2015-07-13 14:10:57 +0100906 idx++) {
907 state_type = find_local_state_type(
908 psci_non_cpu_pd_nodes[idx].local_state);
909 INFO(" Domain Node : Level %u, parent_node %d,"
910 " State %s (0x%x)\n",
911 psci_non_cpu_pd_nodes[idx].level,
912 psci_non_cpu_pd_nodes[idx].parent_node,
913 psci_state_type_str[state_type],
914 psci_non_cpu_pd_nodes[idx].local_state);
915 }
916
Pankaj Gupta02c35682019-10-15 15:44:45 +0530917 for (idx = 0; idx < psci_plat_core_count; idx++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100918 state = psci_get_cpu_local_state_by_idx(idx);
919 state_type = find_local_state_type(state);
Soby Mathewa0fedc42016-06-16 14:52:04 +0100920 INFO(" CPU Node : MPID 0x%llx, parent_node %d,"
Soby Mathew981487a2015-07-13 14:10:57 +0100921 " State %s (0x%x)\n",
Soby Mathewa0fedc42016-06-16 14:52:04 +0100922 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr,
Soby Mathew981487a2015-07-13 14:10:57 +0100923 psci_cpu_pd_nodes[idx].parent_node,
924 psci_state_type_str[state_type],
925 psci_get_cpu_local_state_by_idx(idx));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100926 }
927#endif
928}
Soby Mathew981487a2015-07-13 14:10:57 +0100929
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000930/******************************************************************************
931 * Return whether any secondaries were powered up with CPU_ON call. A CPU that
932 * have ever been powered up would have set its MPDIR value to something other
933 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to
934 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is
935 * meaningful only when called on the primary CPU during early boot.
936 *****************************************************************************/
937int psci_secondaries_brought_up(void)
938{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100939 unsigned int idx, n_valid = 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000940
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100941 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) {
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000942 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR)
943 n_valid++;
944 }
945
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100946 assert(n_valid > 0U);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000947
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100948 return (n_valid > 1U) ? 1 : 0;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000949}
950
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000951/*******************************************************************************
952 * Initiate power down sequence, by calling power down operations registered for
953 * this CPU.
954 ******************************************************************************/
955void psci_do_pwrdown_sequence(unsigned int power_level)
956{
957#if HW_ASSISTED_COHERENCY
958 /*
959 * With hardware-assisted coherency, the CPU drivers only initiate the
960 * power down sequence, without performing cache-maintenance operations
Andrew F. Davis564f9542018-08-30 12:08:01 -0500961 * in software. Data caches enabled both before and after this call.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000962 */
963 prepare_cpu_pwr_dwn(power_level);
964#else
965 /*
966 * Without hardware-assisted coherency, the CPU drivers disable data
Andrew F. Davis564f9542018-08-30 12:08:01 -0500967 * caches, then perform cache-maintenance operations in software.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000968 *
Andrew F. Davis564f9542018-08-30 12:08:01 -0500969 * This also calls prepare_cpu_pwr_dwn() to initiate power down
970 * sequence, but that function will return with data caches disabled.
971 * We must ensure that the stack memory is flushed out to memory before
972 * we start popping from it again.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000973 */
974 psci_do_pwrdown_cache_maintenance(power_level);
975#endif
976}
Sandeep Tripathy12030042020-08-17 20:22:13 +0530977
978/*******************************************************************************
979 * This function invokes the callback 'stop_func()' with the 'mpidr' of each
980 * online PE. Caller can pass suitable method to stop a remote core.
981 *
982 * 'wait_ms' is the timeout value in milliseconds for the other cores to
983 * transition to power down state. Passing '0' makes it non-blocking.
984 *
985 * The function returns 'PSCI_E_DENIED' if some cores failed to stop within the
986 * given timeout.
987 ******************************************************************************/
988int psci_stop_other_cores(unsigned int wait_ms,
989 void (*stop_func)(u_register_t mpidr))
990{
991 unsigned int idx, this_cpu_idx;
992
993 this_cpu_idx = plat_my_core_pos();
994
995 /* Invoke stop_func for each core */
996 for (idx = 0U; idx < psci_plat_core_count; idx++) {
997 /* skip current CPU */
998 if (idx == this_cpu_idx) {
999 continue;
1000 }
1001
1002 /* Check if the CPU is ON */
1003 if (psci_get_aff_info_state_by_idx(idx) == AFF_STATE_ON) {
1004 (*stop_func)(psci_cpu_pd_nodes[idx].mpidr);
1005 }
1006 }
1007
1008 /* Need to wait for other cores to shutdown */
1009 if (wait_ms != 0U) {
1010 while ((wait_ms-- != 0U) && (psci_is_last_on_cpu() != 0U)) {
1011 mdelay(1U);
1012 }
1013
1014 if (psci_is_last_on_cpu() != 0U) {
1015 WARN("Failed to stop all cores!\n");
1016 psci_print_power_domain_map();
1017 return PSCI_E_DENIED;
1018 }
1019 }
1020
1021 return PSCI_E_SUCCESS;
1022}