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Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
Jiafei Pan43a7bf42018-03-21 07:20:09 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef EL3_COMMON_MACROS_S
8#define EL3_COMMON_MACROS_S
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01009
10#include <arch.h>
11#include <asm_macros.S>
12
13 /*
14 * Helper macro to initialise EL3 registers we care about.
15 */
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000016 .macro el3_arch_init_common
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010017 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010018 * SCTLR_EL3 has already been initialised - read current value before
19 * modifying.
20 *
21 * SCTLR_EL3.I: Enable the instruction cache.
22 *
Qixiang Xu3cc39172018-03-05 09:31:11 +080023 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
David Cunadofee86532017-04-13 22:38:29 +010024 * exception is generated if a load or store instruction executed at
25 * EL3 uses the SP as the base address and the SP is not aligned to a
26 * 16-byte boundary.
27 *
28 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
29 * load or store one or more registers have an alignment check that the
30 * address being accessed is aligned to the size of the data element(s)
31 * being accessed.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010032 * ---------------------------------------------------------------------
33 */
34 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
35 mrs x0, sctlr_el3
36 orr x0, x0, x1
37 msr sctlr_el3, x0
38 isb
39
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090040#ifdef IMAGE_BL31
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010041 /* ---------------------------------------------------------------------
42 * Initialise the per-cpu cache pointer to the CPU.
43 * This is done early to enable crash reporting to have access to crash
44 * stack. Since crash reporting depends on cpu_data to report the
45 * unhandled exception, not doing so can lead to recursive exceptions
46 * due to a NULL TPIDR_EL3.
47 * ---------------------------------------------------------------------
48 */
49 bl init_cpu_data_ptr
50#endif /* IMAGE_BL31 */
51
52 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010053 * Initialise SCR_EL3, setting all fields rather than relying on hw.
54 * All fields are architecturally UNKNOWN on reset. The following fields
55 * do not change during the TF lifetime. The remaining fields are set to
56 * zero here but are updated ahead of transitioning to a lower EL in the
57 * function cm_init_context_common().
58 *
59 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
60 * EL2, EL1 and EL0 are not trapped to EL3.
61 *
62 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
63 * EL2, EL1 and EL0 are not trapped to EL3.
64 *
65 * SCR_EL3.SIF: Set to one to disable instruction fetches from
66 * Non-secure memory.
67 *
68 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
69 * both Security states and both Execution states.
70 *
71 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
72 * to EL3 when executing at any EL.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +010073 *
74 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature,
75 * disable traps to EL3 when accessing key registers or using pointer
76 * authentication instructions from lower ELs.
Gerald Lejeune632d6df2016-03-22 09:29:23 +010077 * ---------------------------------------------------------------------
78 */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +010079 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | \
80 SCR_API_BIT | SCR_APK_BIT) \
David Cunadofee86532017-04-13 22:38:29 +010081 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
Gerald Lejeune632d6df2016-03-22 09:29:23 +010082 msr scr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000083
84 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010085 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
86 * Some fields are architecturally UNKNOWN on reset.
87 *
88 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
89 * Debug exceptions, other than Breakpoint Instruction exceptions, are
90 * disabled from all ELs in Secure state.
91 *
92 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
93 * privileged debug from S-EL1.
94 *
95 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
96 * access to the powerdown debug registers do not trap to EL3.
97 *
98 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
99 * debug registers, other than those registers that are controlled by
100 * MDCR_EL3.TDOSA.
101 *
102 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
103 * accesses to all Performance Monitors registers do not trap to EL3.
David Cunado5f55e282016-10-31 17:37:34 +0000104 * ---------------------------------------------------------------------
105 */
David Cunadofee86532017-04-13 22:38:29 +0100106 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \
107 & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
dp-arm595d0d52017-02-08 11:51:50 +0000108 msr mdcr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +0000109
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100110 /* ---------------------------------------------------------------------
111 * Enable External Aborts and SError Interrupts now that the exception
112 * vectors have been setup.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100113 * ---------------------------------------------------------------------
114 */
115 msr daifclr, #DAIF_ABT_BIT
116
117 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100118 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
119 * All fields are architecturally UNKNOWN on reset.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100120 *
David Cunadofee86532017-04-13 22:38:29 +0100121 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
122 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100123 *
David Cunadofee86532017-04-13 22:38:29 +0100124 * CPTR_EL3.TTA: Set to zero so that System register accesses to the
125 * trace registers do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100126 *
David Cunadoce88eee2017-10-20 11:30:57 +0100127 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
128 * by Advanced SIMD, floating-point or SVE instructions (if implemented)
129 * do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100130 */
David Cunadofee86532017-04-13 22:38:29 +0100131 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100132 msr cptr_el3, x0
133 .endm
134
135/* -----------------------------------------------------------------------------
136 * This is the super set of actions that need to be performed during a cold boot
Juan Castillo7d199412015-12-14 09:35:25 +0000137 * or a warm boot in EL3. This code is shared by BL1 and BL31.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100138 *
139 * This macro will always perform reset handling, architectural initialisations
140 * and stack setup. The rest of the actions are optional because they might not
141 * be needed, depending on the context in which this macro is called. This is
142 * why this macro is parameterised ; each parameter allows to enable/disable
143 * some actions.
144 *
David Cunadofee86532017-04-13 22:38:29 +0100145 * _init_sctlr:
146 * Whether the macro needs to initialise SCTLR_EL3, including configuring
147 * the endianness of data accesses.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100148 *
149 * _warm_boot_mailbox:
150 * Whether the macro needs to detect the type of boot (cold/warm). The
151 * detection is based on the platform entrypoint address : if it is zero
152 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
153 * this macro jumps on the platform entrypoint address.
154 *
155 * _secondary_cold_boot:
156 * Whether the macro needs to identify the CPU that is calling it: primary
157 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
158 * the platform initialisations, while the secondaries will be put in a
159 * platform-specific state in the meantime.
160 *
161 * If the caller knows this macro will only be called by the primary CPU
162 * then this parameter can be defined to 0 to skip this step.
163 *
164 * _init_memory:
165 * Whether the macro needs to initialise the memory.
166 *
167 * _init_c_runtime:
168 * Whether the macro needs to initialise the C runtime environment.
169 *
170 * _exception_vectors:
171 * Address of the exception vectors to program in the VBAR_EL3 register.
172 * -----------------------------------------------------------------------------
173 */
174 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100175 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100176 _init_memory, _init_c_runtime, _exception_vectors
177
David Cunadofee86532017-04-13 22:38:29 +0100178 .if \_init_sctlr
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100179 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100180 * This is the initialisation of SCTLR_EL3 and so must ensure
181 * that all fields are explicitly set rather than relying on hw.
182 * Some fields reset to an IMPLEMENTATION DEFINED value and
183 * others are architecturally UNKNOWN on reset.
184 *
185 * SCTLR.EE: Set the CPU endianness before doing anything that
186 * might involve memory reads or writes. Set to zero to select
187 * Little Endian.
188 *
189 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
190 * force all memory regions that are writeable to be treated as
191 * XN (Execute-never). Set to zero so that this control has no
192 * effect on memory access permissions.
193 *
Qixiang Xu3cc39172018-03-05 09:31:11 +0800194 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
David Cunadofee86532017-04-13 22:38:29 +0100195 *
196 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100197 * -------------------------------------------------------------
198 */
David Cunadofee86532017-04-13 22:38:29 +0100199 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
200 | SCTLR_SA_BIT | SCTLR_A_BIT))
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100201 msr sctlr_el3, x0
202 isb
David Cunadofee86532017-04-13 22:38:29 +0100203 .endif /* _init_sctlr */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100204
205 .if \_warm_boot_mailbox
206 /* -------------------------------------------------------------
207 * This code will be executed for both warm and cold resets.
208 * Now is the time to distinguish between the two.
209 * Query the platform entrypoint address and if it is not zero
210 * then it means it is a warm boot so jump to this address.
211 * -------------------------------------------------------------
212 */
Soby Mathew3700a922015-07-13 11:21:11 +0100213 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100214 cbz x0, do_cold_boot
215 br x0
216
217 do_cold_boot:
218 .endif /* _warm_boot_mailbox */
219
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000220 /* ---------------------------------------------------------------------
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000221 * Set the exception vectors.
222 * ---------------------------------------------------------------------
223 */
224 adr x0, \_exception_vectors
225 msr vbar_el3, x0
226 isb
227
228 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000229 * It is a cold boot.
230 * Perform any processor specific actions upon reset e.g. cache, TLB
231 * invalidations etc.
232 * ---------------------------------------------------------------------
233 */
234 bl reset_handler
235
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000236 el3_arch_init_common
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000237
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100238 .if \_secondary_cold_boot
239 /* -------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000240 * Check if this is a primary or secondary CPU cold boot.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100241 * The primary CPU will set up the platform while the
242 * secondaries are placed in a platform-specific state until the
243 * primary CPU performs the necessary actions to bring them out
244 * of that state and allows entry into the OS.
245 * -------------------------------------------------------------
246 */
Soby Mathew3700a922015-07-13 11:21:11 +0100247 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100248 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100249
250 /* This is a cold boot on a secondary CPU */
251 bl plat_secondary_cold_boot_setup
252 /* plat_secondary_cold_boot_setup() is not supposed to return */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000253 bl el3_panic
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100254
255 do_primary_cold_boot:
256 .endif /* _secondary_cold_boot */
257
258 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000259 * Initialize memory now. Secondary CPU initialization won't get to this
260 * point.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100261 * ---------------------------------------------------------------------
262 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100263
264 .if \_init_memory
265 bl platform_mem_init
266 .endif /* _init_memory */
267
268 /* ---------------------------------------------------------------------
269 * Init C runtime environment:
270 * - Zero-initialise the NOBITS sections. There are 2 of them:
271 * - the .bss section;
272 * - the coherent memory section (if any).
273 * - Relocate the data section from ROM to RAM, if required.
274 * ---------------------------------------------------------------------
275 */
276 .if \_init_c_runtime
Roberto Vargase0e99462017-10-30 14:43:43 +0000277#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
Achin Guptae9c4a642015-09-11 16:03:13 +0100278 /* -------------------------------------------------------------
279 * Invalidate the RW memory used by the BL31 image. This
280 * includes the data and NOBITS sections. This is done to
281 * safeguard against possible corruption of this memory by
282 * dirty cache lines in a system cache as a result of use by
283 * an earlier boot loader stage.
284 * -------------------------------------------------------------
285 */
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100286 adrp x0, __RW_START__
287 add x0, x0, :lo12:__RW_START__
288 adrp x1, __RW_END__
289 add x1, x1, :lo12:__RW_END__
Achin Guptae9c4a642015-09-11 16:03:13 +0100290 sub x1, x1, x0
291 bl inv_dcache_range
Roberto Vargase0e99462017-10-30 14:43:43 +0000292#endif
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100293 adrp x0, __BSS_START__
294 add x0, x0, :lo12:__BSS_START__
Achin Guptae9c4a642015-09-11 16:03:13 +0100295
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100296 adrp x1, __BSS_END__
297 add x1, x1, :lo12:__BSS_END__
298 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000299 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100300
301#if USE_COHERENT_MEM
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100302 adrp x0, __COHERENT_RAM_START__
303 add x0, x0, :lo12:__COHERENT_RAM_START__
304 adrp x1, __COHERENT_RAM_END_UNALIGNED__
305 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
306 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000307 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100308#endif
309
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000310#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100311 adrp x0, __DATA_RAM_START__
312 add x0, x0, :lo12:__DATA_RAM_START__
313 adrp x1, __DATA_ROM_START__
314 add x1, x1, :lo12:__DATA_ROM_START__
315 adrp x2, __DATA_RAM_END__
316 add x2, x2, :lo12:__DATA_RAM_END__
317 sub x2, x2, x0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100318 bl memcpy16
319#endif
320 .endif /* _init_c_runtime */
321
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100322 /* ---------------------------------------------------------------------
323 * Use SP_EL0 for the C runtime stack.
324 * ---------------------------------------------------------------------
325 */
326 msr spsel, #0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100327
328 /* ---------------------------------------------------------------------
329 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
330 * the MMU is enabled. There is no risk of reading stale stack memory
331 * after enabling the MMU as only the primary CPU is running at the
332 * moment.
333 * ---------------------------------------------------------------------
334 */
Soby Mathew3700a922015-07-13 11:21:11 +0100335 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000336
337#if STACK_PROTECTOR_ENABLED
338 .if \_init_c_runtime
339 bl update_stack_protector_canary
340 .endif /* _init_c_runtime */
341#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100342 .endm
343
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000344#endif /* EL3_COMMON_MACROS_S */