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Yann Gautier66386952018-07-05 16:49:51 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
Yann Gautier2e286922019-03-11 10:04:38 +01003 * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
Yann Gautier66386952018-07-05 16:49:51 +02004 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Yann Gautier66386952018-07-05 16:49:51 +02006/dts-v1/;
7
Yann Gautier4ede20a2020-09-18 15:04:14 +02008#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxaa-pinctrl.dtsi"
12#include <dt-bindings/clock/stm32mp1-clksrc.h>
13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
Yann Gautier66386952018-07-05 16:49:51 +020014
15/ {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010016 model = "STMicroelectronics STM32MP157C eval daughter";
Yann Gautier66386952018-07-05 16:49:51 +020017 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18
19 chosen {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010020 stdout-path = "serial0:115200n8";
Yann Gautier66386952018-07-05 16:49:51 +020021 };
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010022
Yann Gautier4ede20a2020-09-18 15:04:14 +020023
24 memory@c0000000 {
25 device_type = "memory";
26 reg = <0xC0000000 0x40000000>;
27 };
28
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010029 aliases {
30 serial0 = &uart4;
31 };
32};
33
Yann Gautier4ede20a2020-09-18 15:04:14 +020034&bsec {
35 board_id: board_id@ec {
36 reg = <0xec 0x4>;
37 status = "okay";
38 secure-status = "okay";
39 };
40};
41
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010042&clk_hse {
43 st,digbypass;
Yann Gautier66386952018-07-05 16:49:51 +020044};
45
Yann Gautier4ede20a2020-09-18 15:04:14 +020046&cpu0 {
47 cpu-supply = <&vddcore>;
48};
49
50&cpu1 {
51 cpu-supply = <&vddcore>;
52};
53
54&cryp1 {
55 status="okay";
56};
57
Yann Gautier66386952018-07-05 16:49:51 +020058&i2c4 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c4_pins_a>;
61 i2c-scl-rising-time-ns = <185>;
62 i2c-scl-falling-time-ns = <20>;
Yann Gautier4ede20a2020-09-18 15:04:14 +020063 clock-frequency = <400000>;
Yann Gautier66386952018-07-05 16:49:51 +020064 status = "okay";
65
Yann Gautiera45433b2019-01-16 18:31:00 +010066 pmic: stpmic@33 {
67 compatible = "st,stpmic1";
Yann Gautier66386952018-07-05 16:49:51 +020068 reg = <0x33>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010069 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
Yann Gautier66386952018-07-05 16:49:51 +020072 status = "okay";
73
Yann Gautier66386952018-07-05 16:49:51 +020074 regulators {
Yann Gautiera45433b2019-01-16 18:31:00 +010075 compatible = "st,stpmic1-regulators";
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010076 ldo1-supply = <&v3v3>;
77 ldo2-supply = <&v3v3>;
78 ldo3-supply = <&vdd_ddr>;
79 ldo5-supply = <&v3v3>;
80 ldo6-supply = <&v3v3>;
Yann Gautier4ede20a2020-09-18 15:04:14 +020081 pwr_sw1-supply = <&bst_out>;
82 pwr_sw2-supply = <&bst_out>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010083
84 vddcore: buck1 {
85 regulator-name = "vddcore";
Yann Gautierf3928f62019-02-14 11:15:03 +010086 regulator-min-microvolt = <1200000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010087 regulator-max-microvolt = <1350000>;
88 regulator-always-on;
89 regulator-initial-mode = <0>;
90 regulator-over-current-protection;
91 };
92
93 vdd_ddr: buck2 {
94 regulator-name = "vdd_ddr";
95 regulator-min-microvolt = <1350000>;
96 regulator-max-microvolt = <1350000>;
97 regulator-always-on;
98 regulator-initial-mode = <0>;
99 regulator-over-current-protection;
100 };
101
102 vdd: buck3 {
103 regulator-name = "vdd";
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 regulator-always-on;
107 st,mask-reset;
108 regulator-initial-mode = <0>;
109 regulator-over-current-protection;
110 };
111
Yann Gautier66386952018-07-05 16:49:51 +0200112 v3v3: buck4 {
113 regulator-name = "v3v3";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100116 regulator-always-on;
Yann Gautier66386952018-07-05 16:49:51 +0200117 regulator-over-current-protection;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100118 regulator-initial-mode = <0>;
119 };
120
121 vdda: ldo1 {
122 regulator-name = "vdda";
123 regulator-min-microvolt = <2900000>;
124 regulator-max-microvolt = <2900000>;
125 };
Yann Gautier66386952018-07-05 16:49:51 +0200126
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100127 v2v8: ldo2 {
128 regulator-name = "v2v8";
129 regulator-min-microvolt = <2800000>;
130 regulator-max-microvolt = <2800000>;
Yann Gautier66386952018-07-05 16:49:51 +0200131 };
132
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100133 vtt_ddr: ldo3 {
134 regulator-name = "vtt_ddr";
135 regulator-min-microvolt = <500000>;
136 regulator-max-microvolt = <750000>;
137 regulator-always-on;
138 regulator-over-current-protection;
139 };
140
141 vdd_usb: ldo4 {
142 regulator-name = "vdd_usb";
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100143 };
144
Yann Gautier66386952018-07-05 16:49:51 +0200145 vdd_sd: ldo5 {
146 regulator-name = "vdd_sd";
147 regulator-min-microvolt = <2900000>;
148 regulator-max-microvolt = <2900000>;
149 regulator-boot-on;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100150 };
Yann Gautier66386952018-07-05 16:49:51 +0200151
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100152 v1v8: ldo6 {
153 regulator-name = "v1v8";
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <1800000>;
156 };
157
158 vref_ddr: vref_ddr {
159 regulator-name = "vref_ddr";
160 regulator-always-on;
Yann Gautier66386952018-07-05 16:49:51 +0200161 };
Yann Gautier66386952018-07-05 16:49:51 +0200162
Yann Gautier4ede20a2020-09-18 15:04:14 +0200163 bst_out: boost {
164 regulator-name = "bst_out";
165 };
Yann Gautier3edc7c32019-05-20 19:17:08 +0200166
Yann Gautier4ede20a2020-09-18 15:04:14 +0200167 vbus_otg: pwr_sw1 {
168 regulator-name = "vbus_otg";
169 };
Yann Gautier66386952018-07-05 16:49:51 +0200170
Yann Gautier4ede20a2020-09-18 15:04:14 +0200171 vbus_sw: pwr_sw2 {
172 regulator-name = "vbus_sw";
173 regulator-active-discharge = <1>;
174 };
175 };
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100176
Yann Gautier4ede20a2020-09-18 15:04:14 +0200177 onkey {
178 compatible = "st,stpmic1-onkey";
179 power-off-time-sec = <10>;
180 status = "okay";
181 };
Yann Gautier66386952018-07-05 16:49:51 +0200182
Yann Gautier4ede20a2020-09-18 15:04:14 +0200183 watchdog {
184 compatible = "st,stpmic1-wdt";
185 status = "disabled";
186 };
187 };
Yann Gautier66386952018-07-05 16:49:51 +0200188};
189
Yann Gautier4ede20a2020-09-18 15:04:14 +0200190&iwdg2 {
191 timeout-sec = <32>;
Yann Gautier66386952018-07-05 16:49:51 +0200192 status = "okay";
193};
194
Yann Gautier4ede20a2020-09-18 15:04:14 +0200195&pwr_regulators {
196 vdd-supply = <&vdd>;
197 vdd_3v3_usbfs-supply = <&vdd_usb>;
Yann Gautier66386952018-07-05 16:49:51 +0200198};
199
Yann Gautier66386952018-07-05 16:49:51 +0200200&rcc {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100201 secure-status = "disabled";
Yann Gautier66386952018-07-05 16:49:51 +0200202 st,clksrc = <
203 CLK_MPU_PLL1P
204 CLK_AXI_PLL2P
Yann Gautiered342322019-02-15 17:33:27 +0100205 CLK_MCU_PLL3P
Yann Gautier66386952018-07-05 16:49:51 +0200206 CLK_PLL12_HSE
207 CLK_PLL3_HSE
208 CLK_PLL4_HSE
209 CLK_RTC_LSE
210 CLK_MCO1_DISABLED
211 CLK_MCO2_DISABLED
212 >;
213
214 st,clkdiv = <
215 1 /*MPU*/
216 0 /*AXI*/
Yann Gautiered342322019-02-15 17:33:27 +0100217 0 /*MCU*/
Yann Gautier66386952018-07-05 16:49:51 +0200218 1 /*APB1*/
219 1 /*APB2*/
220 1 /*APB3*/
221 1 /*APB4*/
222 2 /*APB5*/
223 23 /*RTC*/
224 0 /*MCO1*/
225 0 /*MCO2*/
226 >;
227
228 st,pkcs = <
229 CLK_CKPER_HSE
230 CLK_FMC_ACLK
231 CLK_QSPI_ACLK
232 CLK_ETH_DISABLED
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100233 CLK_SDMMC12_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200234 CLK_DSI_DSIPLL
235 CLK_STGEN_HSE
236 CLK_USBPHY_HSE
237 CLK_SPI2S1_PLL3Q
238 CLK_SPI2S23_PLL3Q
239 CLK_SPI45_HSI
240 CLK_SPI6_HSI
241 CLK_I2C46_HSI
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100242 CLK_SDMMC3_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200243 CLK_USBO_USBPHY
244 CLK_ADC_CKPER
245 CLK_CEC_LSE
246 CLK_I2C12_HSI
247 CLK_I2C35_HSI
248 CLK_UART1_HSI
249 CLK_UART24_HSI
250 CLK_UART35_HSI
251 CLK_UART6_HSI
252 CLK_UART78_HSI
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100253 CLK_SPDIF_PLL4P
Antonio Borneodd445ab2019-07-29 14:46:16 +0200254 CLK_FDCAN_PLL4R
Yann Gautier66386952018-07-05 16:49:51 +0200255 CLK_SAI1_PLL3Q
256 CLK_SAI2_PLL3Q
257 CLK_SAI3_PLL3Q
258 CLK_SAI4_PLL3Q
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100259 CLK_RNG1_LSI
260 CLK_RNG2_LSI
Yann Gautier66386952018-07-05 16:49:51 +0200261 CLK_LPTIM1_PCLK1
262 CLK_LPTIM23_PCLK3
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100263 CLK_LPTIM45_LSE
Yann Gautier66386952018-07-05 16:49:51 +0200264 >;
265
266 /* VCO = 1300.0 MHz => P = 650 (CPU) */
267 pll1: st,pll@0 {
268 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
269 frac = < 0x800 >;
270 };
271
272 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
273 pll2: st,pll@1 {
274 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
275 frac = < 0x1400 >;
276 };
277
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100278 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
Yann Gautier66386952018-07-05 16:49:51 +0200279 pll3: st,pll@2 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100280 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
281 frac = < 0x1a04 >;
Yann Gautier66386952018-07-05 16:49:51 +0200282 };
283
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100284 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
Yann Gautier66386952018-07-05 16:49:51 +0200285 pll4: st,pll@3 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100286 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
Yann Gautier66386952018-07-05 16:49:51 +0200287 };
288};
289
Yann Gautier4ede20a2020-09-18 15:04:14 +0200290&rng1 {
291 status = "okay";
292};
293
294&rtc {
295 status = "okay";
296};
297
298&sdmmc1 {
299 pinctrl-names = "default";
300 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
301 disable-wp;
302 st,sig-dir;
303 st,neg-edge;
304 st,use-ckin;
305 bus-width = <4>;
306 vmmc-supply = <&vdd_sd>;
307 sd-uhs-sdr12;
308 sd-uhs-sdr25;
309 sd-uhs-sdr50;
310 sd-uhs-ddr50;
311 status = "okay";
312};
313
314&sdmmc2 {
315 pinctrl-names = "default";
316 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
317 non-removable;
318 no-sd;
319 no-sdio;
320 st,neg-edge;
321 bus-width = <8>;
322 vmmc-supply = <&v3v3>;
323 vqmmc-supply = <&vdd>;
324 mmc-ddr-3_3v;
325 status = "okay";
326};
327
328&uart4 {
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart4_pins_a>;
331 status = "okay";
Yann Gautier990ecea2019-06-04 17:24:36 +0200332};