Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #ifndef __PLAT_ARM_H__ |
| 31 | #define __PLAT_ARM_H__ |
| 32 | |
| 33 | #include <bakery_lock.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <cassert.h> |
| 36 | #include <cpu_data.h> |
| 37 | #include <stdint.h> |
Soby Mathew | fe3b576 | 2015-10-27 10:31:35 +0000 | [diff] [blame] | 38 | #include <xlat_tables.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 39 | |
| 40 | |
| 41 | /* |
| 42 | * Extern declarations common to ARM standard platforms |
| 43 | */ |
| 44 | extern const mmap_region_t plat_arm_mmap[]; |
| 45 | |
| 46 | #define ARM_CASSERT_MMAP \ |
| 47 | CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ |
| 48 | <= MAX_MMAP_REGIONS, \ |
| 49 | assert_max_mmap_regions); |
| 50 | |
| 51 | /* |
| 52 | * Utility functions common to ARM standard platforms |
| 53 | */ |
| 54 | |
| 55 | void arm_configure_mmu_el1(unsigned long total_base, |
| 56 | unsigned long total_size, |
| 57 | unsigned long ro_start, |
| 58 | unsigned long ro_limit |
| 59 | #if USE_COHERENT_MEM |
| 60 | , unsigned long coh_start, |
| 61 | unsigned long coh_limit |
| 62 | #endif |
| 63 | ); |
| 64 | void arm_configure_mmu_el3(unsigned long total_base, |
| 65 | unsigned long total_size, |
| 66 | unsigned long ro_start, |
| 67 | unsigned long ro_limit |
| 68 | #if USE_COHERENT_MEM |
| 69 | , unsigned long coh_start, |
| 70 | unsigned long coh_limit |
| 71 | #endif |
| 72 | ); |
| 73 | |
| 74 | #if IMAGE_BL31 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 75 | /* |
| 76 | * Use this macro to instantiate lock before it is used in below |
| 77 | * arm_lock_xxx() macros |
| 78 | */ |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 79 | #define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * These are wrapper macros to the Coherent Memory Bakery Lock API. |
| 83 | */ |
| 84 | #define arm_lock_init() bakery_lock_init(&arm_lock) |
| 85 | #define arm_lock_get() bakery_lock_get(&arm_lock) |
| 86 | #define arm_lock_release() bakery_lock_release(&arm_lock) |
| 87 | |
| 88 | #else |
| 89 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 90 | /* |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 91 | * Empty macros for all other BL stages other than BL3-1 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 92 | */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 93 | #define ARM_INSTANTIATE_LOCK |
| 94 | #define arm_lock_init() |
| 95 | #define arm_lock_get() |
| 96 | #define arm_lock_release() |
| 97 | |
| 98 | #endif /* IMAGE_BL31 */ |
| 99 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 100 | #if ARM_RECOM_STATE_ID_ENC |
| 101 | /* |
| 102 | * Macros used to parse state information from State-ID if it is using the |
| 103 | * recommended encoding for State-ID. |
| 104 | */ |
| 105 | #define ARM_LOCAL_PSTATE_WIDTH 4 |
| 106 | #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) |
| 107 | |
| 108 | /* Macros to construct the composite power state */ |
| 109 | |
| 110 | /* Make composite power state parameter till power level 0 */ |
| 111 | #if PSCI_EXTENDED_STATE_ID |
| 112 | |
| 113 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 114 | (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) |
| 115 | #else |
| 116 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 117 | (((lvl0_state) << PSTATE_ID_SHIFT) | \ |
| 118 | ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ |
| 119 | ((type) << PSTATE_TYPE_SHIFT)) |
| 120 | #endif /* __PSCI_EXTENDED_STATE_ID__ */ |
| 121 | |
| 122 | /* Make composite power state parameter till power level 1 */ |
| 123 | #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 124 | (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ |
| 125 | arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) |
| 126 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 127 | /* Make composite power state parameter till power level 2 */ |
| 128 | #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 129 | (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ |
| 130 | arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) |
| 131 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 132 | #endif /* __ARM_RECOM_STATE_ID_ENC__ */ |
| 133 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 134 | |
| 135 | /* CCI utility functions */ |
| 136 | void arm_cci_init(void); |
| 137 | |
| 138 | /* IO storage utility functions */ |
| 139 | void arm_io_setup(void); |
| 140 | |
| 141 | /* Security utility functions */ |
| 142 | void arm_tzc_setup(void); |
| 143 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 144 | /* Systimer utility function */ |
| 145 | void arm_configure_sys_timer(void); |
| 146 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 147 | /* PM utility functions */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 148 | int arm_validate_power_state(unsigned int power_state, |
| 149 | psci_power_state_t *req_state); |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 150 | int arm_validate_ns_entrypoint(uintptr_t entrypoint); |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 151 | void arm_system_pwr_domain_resume(void); |
Sandrine Bailleux | 03897bb | 2015-11-26 16:31:34 +0000 | [diff] [blame] | 152 | void arm_program_trusted_mailbox(uintptr_t address); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 153 | |
| 154 | /* Topology utility function */ |
| 155 | int arm_check_mpidr(u_register_t mpidr); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 156 | |
| 157 | /* BL1 utility functions */ |
| 158 | void arm_bl1_early_platform_setup(void); |
| 159 | void arm_bl1_platform_setup(void); |
| 160 | void arm_bl1_plat_arch_setup(void); |
| 161 | |
| 162 | /* BL2 utility functions */ |
| 163 | void arm_bl2_early_platform_setup(meminfo_t *mem_layout); |
| 164 | void arm_bl2_platform_setup(void); |
| 165 | void arm_bl2_plat_arch_setup(void); |
| 166 | uint32_t arm_get_spsr_for_bl32_entry(void); |
| 167 | uint32_t arm_get_spsr_for_bl33_entry(void); |
| 168 | |
| 169 | /* BL3-1 utility functions */ |
| 170 | void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, |
| 171 | void *plat_params_from_bl2); |
| 172 | void arm_bl31_platform_setup(void); |
| 173 | void arm_bl31_plat_arch_setup(void); |
| 174 | |
| 175 | /* TSP utility functions */ |
| 176 | void arm_tsp_early_platform_setup(void); |
| 177 | |
| 178 | |
| 179 | /* |
| 180 | * Mandatory functions required in ARM standard platforms |
| 181 | */ |
| 182 | void plat_arm_gic_init(void); |
| 183 | void plat_arm_security_setup(void); |
| 184 | void plat_arm_pwrc_setup(void); |
| 185 | |
| 186 | /* |
| 187 | * Optional functions required in ARM standard platforms |
| 188 | */ |
| 189 | void plat_arm_io_setup(void); |
| 190 | int plat_arm_get_alt_image_source( |
Juan Castillo | 3a66aca | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 191 | unsigned int image_id, |
| 192 | uintptr_t *dev_handle, |
| 193 | uintptr_t *image_spec); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 194 | unsigned int plat_arm_calc_core_pos(u_register_t mpidr); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 195 | |
| 196 | |
| 197 | #endif /* __PLAT_ARM_H__ */ |