Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <asm_macros.S> |
| 7 | #include <platform_def.h> |
| 8 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 9 | .weak plat_arm_calc_core_pos |
| 10 | .weak plat_my_core_pos |
Antonio Nino Diaz | e55e85f | 2018-10-16 14:10:15 +0100 | [diff] [blame] | 11 | .globl plat_crash_console_init |
| 12 | .globl plat_crash_console_putc |
| 13 | .globl plat_crash_console_flush |
Sandrine Bailleux | aa94ffa | 2015-07-10 17:33:26 +0100 | [diff] [blame] | 14 | .globl platform_mem_init |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 15 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 16 | |
| 17 | /* ----------------------------------------------------- |
| 18 | * unsigned int plat_my_core_pos(void) |
| 19 | * This function uses the plat_arm_calc_core_pos() |
| 20 | * definition to get the index of the calling CPU. |
| 21 | * ----------------------------------------------------- |
| 22 | */ |
| 23 | func plat_my_core_pos |
| 24 | mrs x0, mpidr_el1 |
| 25 | b plat_arm_calc_core_pos |
| 26 | endfunc plat_my_core_pos |
| 27 | |
| 28 | /* ----------------------------------------------------- |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 29 | * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 30 | * Helper function to calculate the core position. |
| 31 | * With this function: CorePos = (ClusterId * 4) + |
| 32 | * CoreId |
| 33 | * ----------------------------------------------------- |
| 34 | */ |
| 35 | func plat_arm_calc_core_pos |
| 36 | and x1, x0, #MPIDR_CPU_MASK |
| 37 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 38 | add x0, x1, x0, LSR #6 |
| 39 | ret |
| 40 | endfunc plat_arm_calc_core_pos |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 41 | |
| 42 | /* --------------------------------------------- |
| 43 | * int plat_crash_console_init(void) |
| 44 | * Function to initialize the crash console |
| 45 | * without a C Runtime to print crash report. |
Juan Castillo | e7ae6db | 2015-11-26 14:52:15 +0000 | [diff] [blame] | 46 | * Clobber list : x0 - x4 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 47 | * --------------------------------------------- |
| 48 | */ |
| 49 | func plat_crash_console_init |
| 50 | mov_imm x0, PLAT_ARM_CRASH_UART_BASE |
| 51 | mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ |
| 52 | mov_imm x2, ARM_CONSOLE_BAUDRATE |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 53 | b console_pl011_core_init |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 54 | endfunc plat_crash_console_init |
| 55 | |
| 56 | /* --------------------------------------------- |
| 57 | * int plat_crash_console_putc(int c) |
| 58 | * Function to print a character on the crash |
| 59 | * console without a C Runtime. |
| 60 | * Clobber list : x1, x2 |
| 61 | * --------------------------------------------- |
| 62 | */ |
| 63 | func plat_crash_console_putc |
| 64 | mov_imm x1, PLAT_ARM_CRASH_UART_BASE |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 65 | b console_pl011_core_putc |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 66 | endfunc plat_crash_console_putc |
Sandrine Bailleux | aa94ffa | 2015-07-10 17:33:26 +0100 | [diff] [blame] | 67 | |
Antonio Nino Diaz | d3ec543 | 2017-02-17 17:11:27 +0000 | [diff] [blame] | 68 | /* --------------------------------------------- |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 69 | * void plat_crash_console_flush() |
Antonio Nino Diaz | d3ec543 | 2017-02-17 17:11:27 +0000 | [diff] [blame] | 70 | * Function to force a write of all buffered |
| 71 | * data that hasn't been output. |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 72 | * Out : void. |
Jeenu Viswambharan | 46343c0 | 2018-01-25 12:49:57 +0000 | [diff] [blame] | 73 | * Clobber list : r0 |
Antonio Nino Diaz | d3ec543 | 2017-02-17 17:11:27 +0000 | [diff] [blame] | 74 | * --------------------------------------------- |
| 75 | */ |
| 76 | func plat_crash_console_flush |
Jeenu Viswambharan | 46343c0 | 2018-01-25 12:49:57 +0000 | [diff] [blame] | 77 | mov_imm x0, PLAT_ARM_CRASH_UART_BASE |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 78 | b console_pl011_core_flush |
Antonio Nino Diaz | d3ec543 | 2017-02-17 17:11:27 +0000 | [diff] [blame] | 79 | endfunc plat_crash_console_flush |
| 80 | |
Sandrine Bailleux | aa94ffa | 2015-07-10 17:33:26 +0100 | [diff] [blame] | 81 | /* --------------------------------------------------------------------- |
| 82 | * We don't need to carry out any memory initialization on ARM |
| 83 | * platforms. The Secure RAM is accessible straight away. |
| 84 | * --------------------------------------------------------------------- |
| 85 | */ |
| 86 | func platform_mem_init |
| 87 | ret |
| 88 | endfunc platform_mem_init |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 89 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 90 | /* |
| 91 | * Need to use coherent stack when ARM Cryptocell is used to autheticate images |
| 92 | * since Cryptocell uses DMA to transfer data and it is not coherent with the |
| 93 | * AP CPU. |
| 94 | */ |
| 95 | #if ARM_CRYPTOCELL_INTEG |
| 96 | #if defined(IMAGE_BL1) || defined(IMAGE_BL2) |
| 97 | .globl plat_get_my_stack |
| 98 | .globl plat_set_my_stack |
| 99 | .local platform_coherent_stacks |
| 100 | |
| 101 | /* ------------------------------------------------------- |
| 102 | * uintptr_t plat_get_my_stack () |
| 103 | * |
| 104 | * For cold-boot BL images, only the primary CPU needs a |
| 105 | * stack. This function returns the stack pointer for a |
| 106 | * stack allocated in coherent memory. |
| 107 | * ------------------------------------------------------- |
| 108 | */ |
| 109 | func plat_get_my_stack |
| 110 | get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE |
| 111 | ret |
| 112 | endfunc plat_get_my_stack |
| 113 | |
| 114 | /* ------------------------------------------------------- |
| 115 | * void plat_set_my_stack () |
| 116 | * |
| 117 | * For cold-boot BL images, only the primary CPU needs a |
| 118 | * stack. This function sets the stack pointer to a stack |
| 119 | * allocated in coherent memory. |
| 120 | * ------------------------------------------------------- |
| 121 | */ |
| 122 | func plat_set_my_stack |
| 123 | get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE |
| 124 | mov sp, x0 |
| 125 | ret |
| 126 | endfunc plat_set_my_stack |
| 127 | |
| 128 | /* ---------------------------------------------------- |
| 129 | * Single cpu stack in coherent memory. |
| 130 | * ---------------------------------------------------- |
| 131 | */ |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame^] | 132 | declare_stack platform_coherent_stacks, .tzfw_coherent_mem, \ |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 133 | PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE |
| 134 | |
| 135 | #endif /* defined(IMAGE_BL1) || defined(IMAGE_BL2) */ |
| 136 | #endif /* ARM_CRYPTOCELL_INTEG */ |