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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <asm_macros.S>
7#include <platform_def.h>
8
Soby Mathewfec4eb72015-07-01 16:16:20 +01009 .weak plat_arm_calc_core_pos
10 .weak plat_my_core_pos
Antonio Nino Diaze55e85f2018-10-16 14:10:15 +010011 .globl plat_crash_console_init
12 .globl plat_crash_console_putc
13 .globl plat_crash_console_flush
Sandrine Bailleuxaa94ffa2015-07-10 17:33:26 +010014 .globl platform_mem_init
Dan Handley9df48042015-03-19 18:58:55 +000015
Soby Mathewfec4eb72015-07-01 16:16:20 +010016
17 /* -----------------------------------------------------
18 * unsigned int plat_my_core_pos(void)
19 * This function uses the plat_arm_calc_core_pos()
20 * definition to get the index of the calling CPU.
21 * -----------------------------------------------------
22 */
23func plat_my_core_pos
24 mrs x0, mpidr_el1
25 b plat_arm_calc_core_pos
26endfunc plat_my_core_pos
27
28 /* -----------------------------------------------------
Soby Mathewa0fedc42016-06-16 14:52:04 +010029 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
Soby Mathewfec4eb72015-07-01 16:16:20 +010030 * Helper function to calculate the core position.
31 * With this function: CorePos = (ClusterId * 4) +
32 * CoreId
33 * -----------------------------------------------------
34 */
35func plat_arm_calc_core_pos
36 and x1, x0, #MPIDR_CPU_MASK
37 and x0, x0, #MPIDR_CLUSTER_MASK
38 add x0, x1, x0, LSR #6
39 ret
40endfunc plat_arm_calc_core_pos
Dan Handley9df48042015-03-19 18:58:55 +000041
42 /* ---------------------------------------------
43 * int plat_crash_console_init(void)
44 * Function to initialize the crash console
45 * without a C Runtime to print crash report.
Juan Castilloe7ae6db2015-11-26 14:52:15 +000046 * Clobber list : x0 - x4
Dan Handley9df48042015-03-19 18:58:55 +000047 * ---------------------------------------------
48 */
49func plat_crash_console_init
50 mov_imm x0, PLAT_ARM_CRASH_UART_BASE
51 mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ
52 mov_imm x2, ARM_CONSOLE_BAUDRATE
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010053 b console_pl011_core_init
Dan Handley9df48042015-03-19 18:58:55 +000054endfunc plat_crash_console_init
55
56 /* ---------------------------------------------
57 * int plat_crash_console_putc(int c)
58 * Function to print a character on the crash
59 * console without a C Runtime.
60 * Clobber list : x1, x2
61 * ---------------------------------------------
62 */
63func plat_crash_console_putc
64 mov_imm x1, PLAT_ARM_CRASH_UART_BASE
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010065 b console_pl011_core_putc
Dan Handley9df48042015-03-19 18:58:55 +000066endfunc plat_crash_console_putc
Sandrine Bailleuxaa94ffa2015-07-10 17:33:26 +010067
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +000068 /* ---------------------------------------------
Jimmy Brisson39f9eee2020-08-05 13:44:05 -050069 * void plat_crash_console_flush()
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +000070 * Function to force a write of all buffered
71 * data that hasn't been output.
Jimmy Brisson39f9eee2020-08-05 13:44:05 -050072 * Out : void.
Jeenu Viswambharan46343c02018-01-25 12:49:57 +000073 * Clobber list : r0
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +000074 * ---------------------------------------------
75 */
76func plat_crash_console_flush
Jeenu Viswambharan46343c02018-01-25 12:49:57 +000077 mov_imm x0, PLAT_ARM_CRASH_UART_BASE
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010078 b console_pl011_core_flush
Antonio Nino Diazd3ec5432017-02-17 17:11:27 +000079endfunc plat_crash_console_flush
80
Sandrine Bailleuxaa94ffa2015-07-10 17:33:26 +010081 /* ---------------------------------------------------------------------
82 * We don't need to carry out any memory initialization on ARM
83 * platforms. The Secure RAM is accessible straight away.
84 * ---------------------------------------------------------------------
85 */
86func platform_mem_init
87 ret
88endfunc platform_mem_init
dp-armee3457b2017-05-23 09:32:49 +010089
Soby Mathew7e4d6652017-05-10 11:50:30 +010090/*
91 * Need to use coherent stack when ARM Cryptocell is used to autheticate images
92 * since Cryptocell uses DMA to transfer data and it is not coherent with the
93 * AP CPU.
94 */
95#if ARM_CRYPTOCELL_INTEG
96#if defined(IMAGE_BL1) || defined(IMAGE_BL2)
97 .globl plat_get_my_stack
98 .globl plat_set_my_stack
99 .local platform_coherent_stacks
100
101 /* -------------------------------------------------------
102 * uintptr_t plat_get_my_stack ()
103 *
104 * For cold-boot BL images, only the primary CPU needs a
105 * stack. This function returns the stack pointer for a
106 * stack allocated in coherent memory.
107 * -------------------------------------------------------
108 */
109func plat_get_my_stack
110 get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
111 ret
112endfunc plat_get_my_stack
113
114 /* -------------------------------------------------------
115 * void plat_set_my_stack ()
116 *
117 * For cold-boot BL images, only the primary CPU needs a
118 * stack. This function sets the stack pointer to a stack
119 * allocated in coherent memory.
120 * -------------------------------------------------------
121 */
122func plat_set_my_stack
123 get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
124 mov sp, x0
125 ret
126endfunc plat_set_my_stack
127
128 /* ----------------------------------------------------
129 * Single cpu stack in coherent memory.
130 * ----------------------------------------------------
131 */
132declare_stack platform_coherent_stacks, tzfw_coherent_mem, \
133 PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
134
135#endif /* defined(IMAGE_BL1) || defined(IMAGE_BL2) */
136#endif /* ARM_CRYPTOCELL_INTEG */