blob: f1d6f878d6e9b6507a256a585cdbb7382d88fa78 [file] [log] [blame]
Ryan Harkin25cff832014-01-13 12:37:03 +00001#
2# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are met:
6#
7# Redistributions of source code must retain the above copyright notice, this
8# list of conditions and the following disclaimer.
9#
10# Redistributions in binary form must reproduce the above copyright notice,
11# this list of conditions and the following disclaimer in the documentation
12# and/or other materials provided with the distribution.
13#
14# Neither the name of ARM nor the names of its contributors may be used
15# to endorse or promote products derived from this software without specific
16# prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28# POSSIBILITY OF SUCH DAMAGE.
29#
30
Sandrine Bailleuxe701e302014-05-20 17:28:25 +010031# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
32# Trusted SRAM is the default.
33TSP_RAM_LOCATION := tsram
34
35ifeq (${TSP_RAM_LOCATION}, tsram)
36 TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
37else ifeq (${TSP_RAM_LOCATION}, tdram)
38 TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
39else
40 $(error "Unsupported TSP_RAM_LOCATION value")
41endif
42
43# Process TSP_RAM_LOCATION_ID flag
44$(eval $(call add_define,TSP_RAM_LOCATION_ID))
45
Soby Mathew5e5c2072014-04-07 15:28:55 +010046PLAT_INCLUDES := -Iplat/fvp/include/
Ryan Harkin25cff832014-01-13 12:37:03 +000047
Dan Handley176e7b42014-04-15 18:20:09 +010048PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
49 drivers/arm/pl011/pl011_console.c \
50 drivers/io/io_fip.c \
51 drivers/io/io_memmap.c \
52 drivers/io/io_semihosting.c \
53 lib/mmio.c \
54 lib/aarch64/sysreg_helpers.S \
55 lib/aarch64/xlat_tables.c \
56 lib/semihosting/semihosting.c \
57 lib/semihosting/aarch64/semihosting_call.S \
58 plat/fvp/plat_io_storage.c
Ryan Harkin25cff832014-01-13 12:37:03 +000059
Dan Handley176e7b42014-04-15 18:20:09 +010060BL1_SOURCES += drivers/arm/cci400/cci400.c \
61 plat/common/aarch64/platform_up_stack.S \
62 plat/fvp/bl1_plat_setup.c \
Dan Handley176e7b42014-04-15 18:20:09 +010063 plat/fvp/aarch64/plat_common.c \
64 plat/fvp/aarch64/plat_helpers.S
Ryan Harkin25cff832014-01-13 12:37:03 +000065
Dan Handley176e7b42014-04-15 18:20:09 +010066BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
67 plat/common/aarch64/platform_up_stack.S \
68 plat/fvp/bl2_plat_setup.c \
69 plat/fvp/plat_security.c \
70 plat/fvp/aarch64/plat_common.c
Ryan Harkin25cff832014-01-13 12:37:03 +000071
Dan Handley176e7b42014-04-15 18:20:09 +010072BL31_SOURCES += drivers/arm/gic/gic_v2.c \
73 drivers/arm/gic/gic_v3.c \
74 drivers/arm/gic/aarch64/gic_v3_sysregs.S \
75 drivers/arm/cci400/cci400.c \
76 plat/common/aarch64/platform_mp_stack.S \
77 plat/fvp/bl31_plat_setup.c \
78 plat/fvp/plat_gic.c \
79 plat/fvp/plat_pm.c \
80 plat/fvp/plat_topology.c \
81 plat/fvp/aarch64/plat_helpers.S \
82 plat/fvp/aarch64/plat_common.c \
83 plat/fvp/drivers/pwrc/fvp_pwrc.c
Vikram Kanigiri96377452014-04-24 11:02:16 +010084
85ifeq (${RESET_TO_BL31}, 1)
86 BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
87 plat/fvp/plat_security.c
88endif
Achin Gupta191e86e2014-05-09 10:03:15 +010089
90# Flag used by the FVP port to determine the version of ARM GIC architecture
91# to use for interrupt management in EL3.
92FVP_GIC_ARCH := 2
93$(eval $(call add_define,FVP_GIC_ARCH))