Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 32 | #include <asm_macros.S> |
Achin Gupta | 4a826dd | 2013-11-25 14:00:56 +0000 | [diff] [blame] | 33 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | .globl enable_irq |
| 35 | .globl disable_irq |
| 36 | |
| 37 | .globl enable_fiq |
| 38 | .globl disable_fiq |
| 39 | |
| 40 | .globl enable_serror |
| 41 | .globl disable_serror |
| 42 | |
Sandrine Bailleux | 3738274 | 2013-11-18 17:26:59 +0000 | [diff] [blame] | 43 | .globl enable_debug_exceptions |
| 44 | .globl disable_debug_exceptions |
| 45 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 46 | .globl read_daif |
| 47 | .globl write_daif |
| 48 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 49 | .globl read_spsr_el1 |
| 50 | .globl read_spsr_el2 |
| 51 | .globl read_spsr_el3 |
| 52 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 53 | .globl write_spsr_el1 |
| 54 | .globl write_spsr_el2 |
| 55 | .globl write_spsr_el3 |
| 56 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 57 | .globl read_elr_el1 |
| 58 | .globl read_elr_el2 |
| 59 | .globl read_elr_el3 |
| 60 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 61 | .globl write_elr_el1 |
| 62 | .globl write_elr_el2 |
| 63 | .globl write_elr_el3 |
| 64 | |
| 65 | .globl get_afflvl_shift |
| 66 | .globl mpidr_mask_lower_afflvls |
| 67 | .globl dsb |
| 68 | .globl isb |
| 69 | .globl sev |
| 70 | .globl wfe |
| 71 | .globl wfi |
| 72 | .globl eret |
| 73 | .globl smc |
| 74 | |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 75 | .globl zeromem16 |
| 76 | .globl memcpy16 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 77 | |
Andrew Thoelke | 438c63a | 2014-04-28 12:06:18 +0100 | [diff] [blame] | 78 | .globl disable_mmu_el3 |
| 79 | .globl disable_mmu_icache_el3 |
| 80 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 82 | func get_afflvl_shift |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | cmp x0, #3 |
| 84 | cinc x0, x0, eq |
| 85 | mov x1, #MPIDR_AFFLVL_SHIFT |
| 86 | lsl x0, x0, x1 |
| 87 | ret |
| 88 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 89 | func mpidr_mask_lower_afflvls |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 90 | cmp x1, #3 |
| 91 | cinc x1, x1, eq |
| 92 | mov x2, #MPIDR_AFFLVL_SHIFT |
| 93 | lsl x2, x1, x2 |
| 94 | lsr x0, x0, x2 |
| 95 | lsl x0, x0, x2 |
| 96 | ret |
| 97 | |
| 98 | /* ----------------------------------------------------- |
| 99 | * Asynchronous exception manipulation accessors |
| 100 | * ----------------------------------------------------- |
| 101 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 102 | func enable_irq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 103 | msr daifclr, #DAIF_IRQ_BIT |
| 104 | ret |
| 105 | |
| 106 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 107 | func enable_fiq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 108 | msr daifclr, #DAIF_FIQ_BIT |
| 109 | ret |
| 110 | |
| 111 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 112 | func enable_serror |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 113 | msr daifclr, #DAIF_ABT_BIT |
| 114 | ret |
| 115 | |
| 116 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 117 | func enable_debug_exceptions |
Sandrine Bailleux | 3738274 | 2013-11-18 17:26:59 +0000 | [diff] [blame] | 118 | msr daifclr, #DAIF_DBG_BIT |
| 119 | ret |
| 120 | |
| 121 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 122 | func disable_irq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 123 | msr daifset, #DAIF_IRQ_BIT |
| 124 | ret |
| 125 | |
| 126 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 127 | func disable_fiq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 128 | msr daifset, #DAIF_FIQ_BIT |
| 129 | ret |
| 130 | |
| 131 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 132 | func disable_serror |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 133 | msr daifset, #DAIF_ABT_BIT |
| 134 | ret |
| 135 | |
| 136 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 137 | func disable_debug_exceptions |
Sandrine Bailleux | 3738274 | 2013-11-18 17:26:59 +0000 | [diff] [blame] | 138 | msr daifset, #DAIF_DBG_BIT |
| 139 | ret |
| 140 | |
| 141 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 142 | func read_daif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 143 | mrs x0, daif |
| 144 | ret |
| 145 | |
| 146 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 147 | func write_daif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 148 | msr daif, x0 |
| 149 | ret |
| 150 | |
| 151 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 152 | func read_spsr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 153 | mrs x0, spsr_el1 |
| 154 | ret |
| 155 | |
| 156 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 157 | func read_spsr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 158 | mrs x0, spsr_el2 |
| 159 | ret |
| 160 | |
| 161 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 162 | func read_spsr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 163 | mrs x0, spsr_el3 |
| 164 | ret |
| 165 | |
| 166 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 167 | func write_spsr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 168 | msr spsr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | ret |
| 170 | |
| 171 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 172 | func write_spsr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 173 | msr spsr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 174 | ret |
| 175 | |
| 176 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 177 | func write_spsr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 178 | msr spsr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 179 | ret |
| 180 | |
| 181 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 182 | func read_elr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 183 | mrs x0, elr_el1 |
| 184 | ret |
| 185 | |
| 186 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 187 | func read_elr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 188 | mrs x0, elr_el2 |
| 189 | ret |
| 190 | |
| 191 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 192 | func read_elr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 193 | mrs x0, elr_el3 |
| 194 | ret |
| 195 | |
| 196 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 197 | func write_elr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 198 | msr elr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 199 | ret |
| 200 | |
| 201 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 202 | func write_elr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | msr elr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 204 | ret |
| 205 | |
| 206 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 207 | func write_elr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 208 | msr elr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 209 | ret |
| 210 | |
| 211 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 212 | func dsb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 213 | dsb sy |
| 214 | ret |
| 215 | |
| 216 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 217 | func isb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 218 | isb |
| 219 | ret |
| 220 | |
| 221 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 222 | func sev |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 223 | sev |
| 224 | ret |
| 225 | |
| 226 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 227 | func wfe |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 228 | wfe |
| 229 | ret |
| 230 | |
| 231 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 232 | func wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 233 | wfi |
| 234 | ret |
| 235 | |
| 236 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 237 | func eret |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 238 | eret |
| 239 | |
| 240 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 241 | func smc |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 242 | smc #0 |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 243 | |
| 244 | /* ----------------------------------------------------------------------- |
| 245 | * void zeromem16(void *mem, unsigned int length); |
| 246 | * |
| 247 | * Initialise a memory region to 0. |
| 248 | * The memory address must be 16-byte aligned. |
| 249 | * ----------------------------------------------------------------------- |
| 250 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 251 | func zeromem16 |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 252 | add x2, x0, x1 |
| 253 | /* zero 16 bytes at a time */ |
| 254 | z_loop16: |
| 255 | sub x3, x2, x0 |
| 256 | cmp x3, #16 |
| 257 | b.lt z_loop1 |
| 258 | stp xzr, xzr, [x0], #16 |
| 259 | b z_loop16 |
| 260 | /* zero byte per byte */ |
| 261 | z_loop1: |
| 262 | cmp x0, x2 |
| 263 | b.eq z_end |
| 264 | strb wzr, [x0], #1 |
| 265 | b z_loop1 |
| 266 | z_end: ret |
| 267 | |
| 268 | |
| 269 | /* -------------------------------------------------------------------------- |
| 270 | * void memcpy16(void *dest, const void *src, unsigned int length) |
| 271 | * |
| 272 | * Copy length bytes from memory area src to memory area dest. |
| 273 | * The memory areas should not overlap. |
| 274 | * Destination and source addresses must be 16-byte aligned. |
| 275 | * -------------------------------------------------------------------------- |
| 276 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 277 | func memcpy16 |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 278 | /* copy 16 bytes at a time */ |
| 279 | m_loop16: |
| 280 | cmp x2, #16 |
| 281 | b.lt m_loop1 |
| 282 | ldp x3, x4, [x1], #16 |
| 283 | stp x3, x4, [x0], #16 |
| 284 | sub x2, x2, #16 |
| 285 | b m_loop16 |
| 286 | /* copy byte per byte */ |
| 287 | m_loop1: |
| 288 | cbz x2, m_end |
| 289 | ldrb w3, [x1], #1 |
| 290 | strb w3, [x0], #1 |
| 291 | subs x2, x2, #1 |
| 292 | b.ne m_loop1 |
| 293 | m_end: ret |
Andrew Thoelke | 438c63a | 2014-04-28 12:06:18 +0100 | [diff] [blame] | 294 | |
| 295 | /* --------------------------------------------------------------------------- |
| 296 | * Disable the MMU at EL3 |
| 297 | * This is implemented in assembler to ensure that the data cache is cleaned |
| 298 | * and invalidated after the MMU is disabled without any intervening cacheable |
| 299 | * data accesses |
| 300 | * --------------------------------------------------------------------------- |
| 301 | */ |
| 302 | |
| 303 | func disable_mmu_el3 |
| 304 | mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) |
| 305 | do_disable_mmu: |
| 306 | mrs x0, sctlr_el3 |
| 307 | bic x0, x0, x1 |
| 308 | msr sctlr_el3, x0 |
| 309 | isb // ensure MMU is off |
| 310 | mov x0, #DCCISW // DCache clean and invalidate |
| 311 | b dcsw_op_all |
| 312 | |
| 313 | |
| 314 | func disable_mmu_icache_el3 |
| 315 | mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) |
| 316 | b do_disable_mmu |
| 317 | |