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Isla Mitchellea84d6b2017-08-03 16:04:46 +01001/*
Govindraj Raja331bdef2023-06-15 17:34:15 -05002 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
Isla Mitchellea84d6b2017-08-03 16:04:46 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CORTEX_A76_H
8#define CORTEX_A76_H
Isla Mitchellea84d6b2017-08-03 16:04:46 +01009
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000010#include <lib/utils_def.h>
11
Isla Mitchellea84d6b2017-08-03 16:04:46 +010012/* Cortex-A76 MIDR for revision 0 */
Bipin Raviee56a8a2022-02-08 19:32:38 -060013#define CORTEX_A76_MIDR U(0x410fd0b0)
14
15/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
16#define CORTEX_A76_BHB_LOOP_COUNT U(24)
Isla Mitchellea84d6b2017-08-03 16:04:46 +010017
18/*******************************************************************************
19 * CPU Extended Control register specific definitions.
20 ******************************************************************************/
Bipin Raviee56a8a2022-02-08 19:32:38 -060021#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
22#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
Isla Mitchellea84d6b2017-08-03 16:04:46 +010023
Bipin Raviee56a8a2022-02-08 19:32:38 -060024#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
25#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
Louis Mayencourtadda9d42019-02-25 11:37:38 +000026
Dimitris Papastamos312e17e2018-05-16 09:59:54 +010027/*******************************************************************************
28 * CPU Auxiliary Control register specific definitions.
29 ******************************************************************************/
Bipin Raviee56a8a2022-02-08 19:32:38 -060030#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0
Louis Mayencourt59fa2182019-02-25 15:17:44 +000031
32#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
33
Bipin Raviee56a8a2022-02-08 19:32:38 -060034#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
Soby Mathew1d3ba1c2019-05-01 09:43:18 +010035
Bipin Raviee56a8a2022-02-08 19:32:38 -060036#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
Dimitris Papastamos312e17e2018-05-16 09:59:54 +010037
Bipin Raviee56a8a2022-02-08 19:32:38 -060038#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
Govindraj Raja331bdef2023-06-15 17:34:15 -050039#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
johpow019603f982020-05-29 14:17:38 -050040
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000041#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
Dimitris Papastamos312e17e2018-05-16 09:59:54 +010042
Bipin Raviee56a8a2022-02-08 19:32:38 -060043#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
Soby Mathew1d3ba1c2019-05-01 09:43:18 +010044
Bipin Raviee56a8a2022-02-08 19:32:38 -060045#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
Soby Mathew1d3ba1c2019-05-01 09:43:18 +010046
47
Isla Mitchellea84d6b2017-08-03 16:04:46 +010048/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
Bipin Raviee56a8a2022-02-08 19:32:38 -060049#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
Isla Mitchellea84d6b2017-08-03 16:04:46 +010050
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000051#endif /* CORTEX_A76_H */