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Pritesh Raithatha537bce42017-01-02 19:43:45 +05301/*
Pritesh Raithatha66f9ff62018-04-19 13:11:43 +05302 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Pritesh Raithatha537bce42017-01-02 19:43:45 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Varun Wadekar00759902017-05-31 11:41:00 -07007#include <common/bl_common.h>
8#include <common/debug.h>
Pritesh Raithatha537bce42017-01-02 19:43:45 +05309#include <smmu.h>
Varun Wadekar00759902017-05-31 11:41:00 -070010#include <tegra_def.h>
Pritesh Raithatha537bce42017-01-02 19:43:45 +053011
Steven Kao7dfbca72017-07-25 12:44:32 +080012#define BOARD_SYSTEM_FPGA_BASE U(1)
13#define BASE_CONFIG_SMMU_DEVICES U(2)
14#define MAX_NUM_SMMU_DEVICES U(3)
15
16static uint32_t tegra_misc_read_32(uint32_t off)
17{
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080018 return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
Steven Kao7dfbca72017-07-25 12:44:32 +080019}
20
Varun Wadekar00759902017-05-31 11:41:00 -070021/*******************************************************************************
Steven Kao7dfbca72017-07-25 12:44:32 +080022 * Handler to return the support SMMU devices number
23 ******************************************************************************/
24uint32_t plat_get_num_smmu_devices(void)
25{
26 uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
Elyes Haouas183638f2023-02-13 10:05:41 +010027 uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >>
Pritesh Raithathafe9635b2017-08-03 19:12:14 +053028 BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
Steven Kao7dfbca72017-07-25 12:44:32 +080029
30 if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
31 ret_num = BASE_CONFIG_SMMU_DEVICES;
32 }
33
34 return ret_num;
Varun Wadekar362a6b22017-11-10 11:04:42 -080035}