Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 8 | #ifndef MARVELL_DEF_H |
| 9 | #define MARVELL_DEF_H |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 10 | |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 11 | #include <platform_def.h> |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 12 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <arch.h> |
| 14 | #include <common/tbbr/tbbr_img_def.h> |
Remi Pommarel | 7459e74 | 2019-07-14 20:34:28 +0200 | [diff] [blame] | 15 | #include <lib/xlat_tables/xlat_tables_v2.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <plat/common/common_def.h> |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 17 | |
| 18 | /**************************************************************************** |
| 19 | * Definitions common to all MARVELL standard platforms |
| 20 | **************************************************************************** |
| 21 | */ |
| 22 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
| 23 | #define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 24 | |
| 25 | #define PLAT_MARVELL_NORTHB_COUNT 1 |
| 26 | |
| 27 | #define PLAT_MARVELL_CLUSTER_COUNT 1 |
| 28 | |
| 29 | #define MARVELL_CACHE_WRITEBACK_SHIFT 6 |
| 30 | |
| 31 | /* |
| 32 | * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. |
| 33 | * The power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 34 | */ |
| 35 | #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 |
| 36 | #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 |
| 37 | #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 |
| 38 | |
| 39 | /* |
| 40 | * Macros for local power states in Marvell platforms encoded by State-ID field |
| 41 | * within the power-state parameter. |
| 42 | */ |
| 43 | /* Local power state for power domains in Run state. */ |
| 44 | #define MARVELL_LOCAL_STATE_RUN 0 |
| 45 | /* Local power state for retention. Valid only for CPU power domains */ |
| 46 | #define MARVELL_LOCAL_STATE_RET 1 |
| 47 | /* Local power state for OFF/power-down. |
| 48 | * Valid for CPU and cluster power domains |
| 49 | */ |
| 50 | #define MARVELL_LOCAL_STATE_OFF 2 |
| 51 | |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 52 | /* This leaves a gap between end of DRAM and start of ROM block */ |
| 53 | #define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ |
| 54 | |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 55 | /* The first 4KB of Trusted SRAM are used as shared memory */ |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 56 | #define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 57 | #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ |
| 58 | |
| 59 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 60 | #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ |
| 61 | MARVELL_SHARED_RAM_SIZE) |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 62 | #define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 63 | MARVELL_SHARED_RAM_SIZE) |
| 64 | |
| 65 | #define MARVELL_DRAM_BASE ULL(0x0) |
| 66 | #define MARVELL_DRAM_SIZE ULL(0x20000000) |
| 67 | #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ |
| 68 | MARVELL_DRAM_SIZE - 1) |
| 69 | |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 70 | #define MARVELL_IRQ_SEC_PHY_TIMER 29 |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 71 | |
| 72 | #define MARVELL_IRQ_SEC_SGI_0 8 |
| 73 | #define MARVELL_IRQ_SEC_SGI_1 9 |
| 74 | #define MARVELL_IRQ_SEC_SGI_2 10 |
| 75 | #define MARVELL_IRQ_SEC_SGI_3 11 |
| 76 | #define MARVELL_IRQ_SEC_SGI_4 12 |
| 77 | #define MARVELL_IRQ_SEC_SGI_5 13 |
| 78 | #define MARVELL_IRQ_SEC_SGI_6 14 |
| 79 | #define MARVELL_IRQ_SEC_SGI_7 15 |
| 80 | |
| 81 | #define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 82 | MARVELL_SHARED_RAM_BASE, \ |
| 83 | MARVELL_SHARED_RAM_SIZE, \ |
| 84 | MT_MEMORY | MT_RW | MT_SECURE) |
| 85 | |
| 86 | #define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ |
| 87 | MARVELL_DRAM_BASE, \ |
| 88 | MARVELL_DRAM_SIZE, \ |
| 89 | MT_MEMORY | MT_RW | MT_NS) |
| 90 | |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 91 | /* |
| 92 | * The number of regions like RO(code), coherent and data required by |
| 93 | * different BL stages which need to be mapped in the MMU. |
| 94 | */ |
| 95 | #if USE_COHERENT_MEM |
| 96 | #define MARVELL_BL_REGIONS 3 |
| 97 | #else |
| 98 | #define MARVELL_BL_REGIONS 2 |
| 99 | #endif |
| 100 | |
| 101 | #define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ |
| 102 | MARVELL_BL_REGIONS) |
| 103 | |
| 104 | #define MARVELL_CONSOLE_BAUDRATE 115200 |
| 105 | |
| 106 | /**************************************************************************** |
| 107 | * Required platform porting definitions common to all MARVELL std. platforms |
| 108 | **************************************************************************** |
| 109 | */ |
| 110 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 111 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 112 | |
| 113 | /* |
| 114 | * This macro defines the deepest retention state possible. A higher state |
| 115 | * id will represent an invalid or a power down state. |
| 116 | */ |
| 117 | #define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET |
| 118 | |
| 119 | /* |
| 120 | * This macro defines the deepest power down states possible. Any state ID |
| 121 | * higher than this is invalid. |
| 122 | */ |
| 123 | #define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF |
| 124 | |
| 125 | |
| 126 | #define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT |
| 127 | |
| 128 | /* |
| 129 | * Some data must be aligned on the biggest cache line size in the platform. |
| 130 | * This is known only to the platform as it might have a combination of |
| 131 | * integrated and external caches. |
| 132 | */ |
| 133 | #define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) |
| 134 | |
| 135 | |
| 136 | /***************************************************************************** |
| 137 | * BL1 specific defines. |
| 138 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 139 | * addresses. |
| 140 | ***************************************************************************** |
| 141 | */ |
| 142 | #define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE |
| 143 | #define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ |
| 144 | + PLAT_MARVELL_TRUSTED_ROM_SIZE) |
| 145 | /* |
| 146 | * Put BL1 RW at the top of the Trusted SRAM. |
| 147 | */ |
| 148 | #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ |
| 149 | MARVELL_BL_RAM_SIZE - \ |
| 150 | PLAT_MARVELL_MAX_BL1_RW_SIZE) |
| 151 | #define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) |
| 152 | |
| 153 | /***************************************************************************** |
| 154 | * BL2 specific defines. |
| 155 | ***************************************************************************** |
| 156 | */ |
| 157 | /* |
| 158 | * Put BL2 just below BL31. |
| 159 | */ |
| 160 | #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) |
| 161 | #define BL2_LIMIT BL31_BASE |
| 162 | |
| 163 | /***************************************************************************** |
| 164 | * BL31 specific defines. |
| 165 | ***************************************************************************** |
| 166 | */ |
| 167 | /* |
| 168 | * Put BL31 at the top of the Trusted SRAM. |
| 169 | */ |
| 170 | #define BL31_BASE (MARVELL_BL_RAM_BASE + \ |
| 171 | MARVELL_BL_RAM_SIZE - \ |
| 172 | PLAT_MARVEL_MAX_BL31_SIZE) |
| 173 | #define BL31_PROGBITS_LIMIT BL1_RW_BASE |
| 174 | #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ |
| 175 | MARVELL_BL_RAM_SIZE) |
| 176 | |
Konstantin Porotchkin | 459366b | 2019-03-14 17:24:40 +0200 | [diff] [blame] | 177 | /***************************************************************************** |
| 178 | * BL32 specific defines. |
| 179 | ***************************************************************************** |
| 180 | */ |
Konstantin Porotchkin | 5f8630b | 2020-06-19 17:48:48 +0200 | [diff] [blame] | 181 | #define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE |
| 182 | #define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) |
Konstantin Porotchkin | 459366b | 2019-03-14 17:24:40 +0200 | [diff] [blame] | 183 | |
| 184 | #ifdef SPD_none |
| 185 | #undef BL32_BASE |
| 186 | #endif /* SPD_none */ |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 187 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 188 | #endif /* MARVELL_DEF_H */ |