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Konstantin Porotchkine7be6e22018-10-08 16:53:09 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef MARVELL_DEF_H
9#define MARVELL_DEF_H
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +030010
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +030011#include <platform_def.h>
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +030012
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <arch.h>
14#include <common/tbbr/tbbr_img_def.h>
15#include <lib/xlat_tables/xlat_tables.h>
16#include <plat/common/common_def.h>
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +030017
18/****************************************************************************
19 * Definitions common to all MARVELL standard platforms
20 ****************************************************************************
21 */
22/* Special value used to verify platform parameters from BL2 to BL31 */
23#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
24
25#define PLAT_MARVELL_NORTHB_COUNT 1
26
27#define PLAT_MARVELL_CLUSTER_COUNT 1
28
29#define MARVELL_CACHE_WRITEBACK_SHIFT 6
30
31/*
32 * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
33 * The power levels have a 1:1 mapping with the MPIDR affinity levels.
34 */
35#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
36#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
37#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
38
39/*
40 * Macros for local power states in Marvell platforms encoded by State-ID field
41 * within the power-state parameter.
42 */
43/* Local power state for power domains in Run state. */
44#define MARVELL_LOCAL_STATE_RUN 0
45/* Local power state for retention. Valid only for CPU power domains */
46#define MARVELL_LOCAL_STATE_RET 1
47/* Local power state for OFF/power-down.
48 * Valid for CPU and cluster power domains
49 */
50#define MARVELL_LOCAL_STATE_OFF 2
51
52/* The first 4KB of Trusted SRAM are used as shared memory */
53#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
54#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
55#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
56
57/* The remaining Trusted SRAM is used to load the BL images */
58#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
59 MARVELL_SHARED_RAM_SIZE)
60#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
61 MARVELL_SHARED_RAM_SIZE)
62
63#define MARVELL_DRAM_BASE ULL(0x0)
64#define MARVELL_DRAM_SIZE ULL(0x20000000)
65#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
66 MARVELL_DRAM_SIZE - 1)
67
68#define MARVELL_IRQ_SEC_PHY_TIMER 29
69
70#define MARVELL_IRQ_SEC_SGI_0 8
71#define MARVELL_IRQ_SEC_SGI_1 9
72#define MARVELL_IRQ_SEC_SGI_2 10
73#define MARVELL_IRQ_SEC_SGI_3 11
74#define MARVELL_IRQ_SEC_SGI_4 12
75#define MARVELL_IRQ_SEC_SGI_5 13
76#define MARVELL_IRQ_SEC_SGI_6 14
77#define MARVELL_IRQ_SEC_SGI_7 15
78
79#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
80 MARVELL_SHARED_RAM_BASE, \
81 MARVELL_SHARED_RAM_SIZE, \
82 MT_MEMORY | MT_RW | MT_SECURE)
83
84#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
85 MARVELL_DRAM_BASE, \
86 MARVELL_DRAM_SIZE, \
87 MT_MEMORY | MT_RW | MT_NS)
88
89
90/*
91 * The number of regions like RO(code), coherent and data required by
92 * different BL stages which need to be mapped in the MMU.
93 */
94#if USE_COHERENT_MEM
95#define MARVELL_BL_REGIONS 3
96#else
97#define MARVELL_BL_REGIONS 2
98#endif
99
100#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \
101 MARVELL_BL_REGIONS)
102
103#define MARVELL_CONSOLE_BAUDRATE 115200
104
105/****************************************************************************
106 * Required platform porting definitions common to all MARVELL std. platforms
107 ****************************************************************************
108 */
109#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
110#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
111
112/*
113 * This macro defines the deepest retention state possible. A higher state
114 * id will represent an invalid or a power down state.
115 */
116#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET
117
118/*
119 * This macro defines the deepest power down states possible. Any state ID
120 * higher than this is invalid.
121 */
122#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF
123
124
125#define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT
126
127/*
128 * Some data must be aligned on the biggest cache line size in the platform.
129 * This is known only to the platform as it might have a combination of
130 * integrated and external caches.
131 */
132#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT)
133
134
135/*****************************************************************************
136 * BL1 specific defines.
137 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
138 * addresses.
139 *****************************************************************************
140 */
141#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE
142#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \
143 + PLAT_MARVELL_TRUSTED_ROM_SIZE)
144/*
145 * Put BL1 RW at the top of the Trusted SRAM.
146 */
147#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \
148 MARVELL_BL_RAM_SIZE - \
149 PLAT_MARVELL_MAX_BL1_RW_SIZE)
150#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
151
152/*****************************************************************************
153 * BL2 specific defines.
154 *****************************************************************************
155 */
156/*
157 * Put BL2 just below BL31.
158 */
159#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
160#define BL2_LIMIT BL31_BASE
161
162/*****************************************************************************
163 * BL31 specific defines.
164 *****************************************************************************
165 */
166/*
167 * Put BL31 at the top of the Trusted SRAM.
168 */
169#define BL31_BASE (MARVELL_BL_RAM_BASE + \
170 MARVELL_BL_RAM_SIZE - \
171 PLAT_MARVEL_MAX_BL31_SIZE)
172#define BL31_PROGBITS_LIMIT BL1_RW_BASE
173#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
174 MARVELL_BL_RAM_SIZE)
175
176
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000177#endif /* MARVELL_DEF_H */