Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 1 | /* |
Manish V Badarkhe | 173c296 | 2022-05-09 21:55:19 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. |
Varun Wadekar | 7559406 | 2020-07-05 13:12:28 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | /* |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 9 | * Driver for GIC-500 and GIC-600 specific features. This driver only |
| 10 | * overrides APIs that are different to those generic ones in GICv3 |
| 11 | * driver. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 12 | * |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 13 | * GIC-600 supports independently power-gating redistributor interface. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 16 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | |
| 18 | #include <arch_helpers.h> |
Claus Pedersen | 785e66c | 2022-09-12 22:42:58 +0000 | [diff] [blame] | 19 | #include <common/debug.h> |
Andre Przywara | daf89a7 | 2021-08-24 10:02:52 +0100 | [diff] [blame] | 20 | #include <drivers/arm/arm_gicv3_common.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 21 | #include <drivers/arm/gicv3.h> |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 22 | |
| 23 | #include "gicv3_private.h" |
| 24 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 25 | /* GIC-600 specific register offsets */ |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 26 | #define GICR_PWRR 0x24U |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 27 | |
| 28 | /* GICR_PWRR fields */ |
Varun Wadekar | 7559406 | 2020-07-05 13:12:28 -0700 | [diff] [blame] | 29 | #define PWRR_RDPD_SHIFT 0 |
| 30 | #define PWRR_RDAG_SHIFT 1 |
| 31 | #define PWRR_RDGPD_SHIFT 2 |
| 32 | #define PWRR_RDGPO_SHIFT 3 |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 33 | |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 34 | #define PWRR_RDPD (1U << PWRR_RDPD_SHIFT) |
| 35 | #define PWRR_RDAG (1U << PWRR_RDAG_SHIFT) |
| 36 | #define PWRR_RDGPD (1U << PWRR_RDGPD_SHIFT) |
| 37 | #define PWRR_RDGPO (1U << PWRR_RDGPO_SHIFT) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 38 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 39 | /* |
| 40 | * Values to write to GICR_PWRR register to power redistributor |
| 41 | * for operating through the core (GICR_PWRR.RDAG = 0) |
| 42 | */ |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 43 | #define PWRR_ON (0U << PWRR_RDPD_SHIFT) |
| 44 | #define PWRR_OFF (1U << PWRR_RDPD_SHIFT) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 45 | |
Manish V Badarkhe | 173c296 | 2022-05-09 21:55:19 +0100 | [diff] [blame] | 46 | static bool gic600_errata_wa_2384374 __unused; |
| 47 | |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 48 | #if GICV3_SUPPORT_GIC600 |
| 49 | |
Andre Przywara | b6c24ce | 2021-07-20 19:20:07 +0100 | [diff] [blame] | 50 | /* GIC-600/700 specific accessor functions */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 51 | static void gicr_write_pwrr(uintptr_t base, unsigned int val) |
| 52 | { |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 53 | mmio_write_32(base + GICR_PWRR, val); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | static uint32_t gicr_read_pwrr(uintptr_t base) |
| 57 | { |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 58 | return mmio_read_32(base + GICR_PWRR); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 59 | } |
| 60 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 61 | static void gicr_wait_group_not_in_transit(uintptr_t base) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 62 | { |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 63 | uint32_t pwrr; |
| 64 | |
| 65 | do { |
| 66 | pwrr = gicr_read_pwrr(base); |
| 67 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 68 | /* Check group not transitioning: RDGPD == RDGPO */ |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 69 | } while (((pwrr & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) != |
| 70 | ((pwrr & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT)); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void gic600_pwr_on(uintptr_t base) |
| 74 | { |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 75 | do { /* Wait until group not transitioning */ |
| 76 | gicr_wait_group_not_in_transit(base); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 77 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 78 | /* Power on redistributor */ |
| 79 | gicr_write_pwrr(base, PWRR_ON); |
| 80 | |
| 81 | /* |
| 82 | * Wait until the power on state is reflected. |
| 83 | * If RDPD == 0 then powered on. |
| 84 | */ |
| 85 | } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | static void gic600_pwr_off(uintptr_t base) |
| 89 | { |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 90 | /* Wait until group not transitioning */ |
| 91 | gicr_wait_group_not_in_transit(base); |
| 92 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 93 | /* Power off redistributor */ |
| 94 | gicr_write_pwrr(base, PWRR_OFF); |
| 95 | |
| 96 | /* |
| 97 | * If this is the last man, turning this redistributor frame off will |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 98 | * result in the group itself being powered off and RDGPD = 1. |
| 99 | * In that case, wait as long as it's in transition, or has aborted |
| 100 | * the transition altogether for any reason. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 101 | */ |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 102 | if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0U) { |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 103 | /* Wait until group not transitioning */ |
| 104 | gicr_wait_group_not_in_transit(base); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 105 | } |
| 106 | } |
| 107 | |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 108 | static uintptr_t get_gicr_base(unsigned int proc_num) |
| 109 | { |
| 110 | uintptr_t gicr_base; |
| 111 | |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 112 | assert(gicv3_driver_data != NULL); |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 113 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 114 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 115 | |
| 116 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 117 | assert(gicr_base != 0UL); |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 118 | |
| 119 | return gicr_base; |
| 120 | } |
| 121 | |
Andre Przywara | 19b2d4e | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 122 | static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base) |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 123 | { |
| 124 | uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR); |
| 125 | |
Andre Przywara | 19b2d4e | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 126 | /* |
Andre Przywara | b6c24ce | 2021-07-20 19:20:07 +0100 | [diff] [blame] | 127 | * The Arm GIC-600 and GIC-700 models have their redistributors |
Andre Przywara | 19b2d4e | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 128 | * powered down at reset. |
| 129 | */ |
Varun Wadekar | 7559406 | 2020-07-05 13:12:28 -0700 | [diff] [blame] | 130 | return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) || |
Andre Przywara | 19b2d4e | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 131 | ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE) || |
Andre Przywara | b6c24ce | 2021-07-20 19:20:07 +0100 | [diff] [blame] | 132 | ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_700)); |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 133 | } |
| 134 | |
Alexei Fedorov | 06d29cf | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 135 | #endif /* GICV3_SUPPORT_GIC600 */ |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 136 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 137 | void gicv3_distif_pre_save(unsigned int proc_num) |
| 138 | { |
| 139 | arm_gicv3_distif_pre_save(proc_num); |
| 140 | } |
| 141 | |
| 142 | void gicv3_distif_post_restore(unsigned int proc_num) |
| 143 | { |
| 144 | arm_gicv3_distif_post_restore(proc_num); |
| 145 | } |
| 146 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 147 | /* |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 148 | * Power off GIC-600 redistributor (if configured and detected) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 149 | */ |
| 150 | void gicv3_rdistif_off(unsigned int proc_num) |
| 151 | { |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 152 | #if GICV3_SUPPORT_GIC600 |
| 153 | uintptr_t gicr_base = get_gicr_base(proc_num); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 154 | |
| 155 | /* Attempt to power redistributor off */ |
Andre Przywara | 19b2d4e | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 156 | if (gicv3_redists_need_power_mgmt(gicr_base)) { |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 157 | gic600_pwr_off(gicr_base); |
| 158 | } |
| 159 | #endif |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | /* |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 163 | * Power on GIC-600 redistributor (if configured and detected) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 164 | */ |
| 165 | void gicv3_rdistif_on(unsigned int proc_num) |
| 166 | { |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 167 | #if GICV3_SUPPORT_GIC600 |
| 168 | uintptr_t gicr_base = get_gicr_base(proc_num); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 169 | |
| 170 | /* Power redistributor on */ |
Andre Przywara | 19b2d4e | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 171 | if (gicv3_redists_need_power_mgmt(gicr_base)) { |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 172 | gic600_pwr_on(gicr_base); |
| 173 | } |
| 174 | #endif |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 175 | } |
Manish V Badarkhe | 173c296 | 2022-05-09 21:55:19 +0100 | [diff] [blame] | 176 | |
| 177 | #if GIC600_ERRATA_WA_2384374 |
| 178 | /******************************************************************************* |
| 179 | * Apply part 2 of workaround for errata-2384374 as per SDEN: |
| 180 | * https://developer.arm.com/documentation/sden892601/latest/ |
| 181 | ******************************************************************************/ |
| 182 | void gicv3_apply_errata_wa_2384374(uintptr_t gicr_base) |
| 183 | { |
| 184 | if (gic600_errata_wa_2384374) { |
| 185 | uint32_t gicr_ctlr_val = gicr_read_ctlr(gicr_base); |
| 186 | |
| 187 | gicr_write_ctlr(gicr_base, gicr_ctlr_val | |
| 188 | (GICR_CTLR_DPG0_BIT | GICR_CTLR_DPG1NS_BIT | |
| 189 | GICR_CTLR_DPG1S_BIT)); |
| 190 | gicr_write_ctlr(gicr_base, gicr_ctlr_val & |
| 191 | ~(GICR_CTLR_DPG0_BIT | GICR_CTLR_DPG1NS_BIT | |
| 192 | GICR_CTLR_DPG1S_BIT)); |
| 193 | } |
| 194 | } |
| 195 | #endif /* GIC600_ERRATA_WA_2384374 */ |
| 196 | |
| 197 | void gicv3_check_erratas_applies(uintptr_t gicd_base) |
| 198 | { |
| 199 | unsigned int gic_prod_id; |
| 200 | uint8_t gic_rev; |
| 201 | |
| 202 | assert(gicd_base != 0UL); |
| 203 | |
| 204 | gicv3_get_component_prodid_rev(gicd_base, &gic_prod_id, &gic_rev); |
| 205 | |
| 206 | /* |
| 207 | * This workaround applicable only to GIC600 and GIC600AE products with |
| 208 | * revision less than r1p6 and r0p2 respectively. |
| 209 | * As per GIC600/GIC600AE specification - |
| 210 | * r1p6 = 0x17 => GICD_IIDR[19:12] |
| 211 | * r0p2 = 0x04 => GICD_IIDR[19:12] |
| 212 | */ |
| 213 | if ((gic_prod_id == GIC_PRODUCT_ID_GIC600) || |
| 214 | (gic_prod_id == GIC_PRODUCT_ID_GIC600AE)) { |
| 215 | if (((gic_prod_id == GIC_PRODUCT_ID_GIC600) && |
| 216 | (gic_rev <= GIC_REV(GIC_VARIANT_R1, GIC_REV_P6))) || |
| 217 | ((gic_prod_id == GIC_PRODUCT_ID_GIC600AE) && |
| 218 | (gic_rev <= GIC_REV(GIC_VARIANT_R0, GIC_REV_P2)))) { |
| 219 | #if GIC600_ERRATA_WA_2384374 |
| 220 | gic600_errata_wa_2384374 = true; |
| 221 | VERBOSE("%s applies\n", |
| 222 | "GIC600/GIC600AE errata workaround 2384374"); |
| 223 | #else |
| 224 | WARN("%s missing\n", |
| 225 | "GIC600/GIC600AE errata workaround 2384374"); |
| 226 | #endif /* GIC600_ERRATA_WA_2384374 */ |
| 227 | } else { |
| 228 | VERBOSE("%s not applies\n", |
| 229 | "GIC600/GIC600AE errata workaround 2384374"); |
| 230 | } |
| 231 | } |
| 232 | } |