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developer8670d252021-03-19 22:13:11 +08001/*
developer479d1ad2022-07-12 10:24:26 +08002 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
developer8670d252021-03-19 22:13:11 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#define PLAT_PRIMARY_CPU 0x0
11
12#define MT_GIC_BASE (0x0C000000)
13#define MCUCFG_BASE (0x0C530000)
14#define IO_PHYS (0x10000000)
15
16/* Aggregate of all devices for MMU mapping */
17#define MTK_DEV_RNG0_BASE IO_PHYS
developerc0cf2742021-06-18 11:33:16 +080018#define MTK_DEV_RNG0_SIZE 0x10000000
developer8670d252021-03-19 22:13:11 +080019#define MTK_DEV_RNG2_BASE MT_GIC_BASE
20#define MTK_DEV_RNG2_SIZE 0x600000
developer037c99f2020-06-15 16:41:03 +080021#define MTK_MCDI_SRAM_BASE 0x11B000
22#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
developer8670d252021-03-19 22:13:11 +080023
developer95d50102021-11-01 16:33:22 +080024#define APUSYS_BASE 0x19000000
25#define APUSYS_SCTRL_REVISER_BASE 0x19021000
26#define APUSYS_SCTRL_REVISER_SIZE 0x1000
27#define APUSYS_APU_S_S_4_BASE 0x190F2000
28#define APUSYS_APU_S_S_4_SIZE 0x1000
29#define APUSYS_APU_PLL_BASE 0x190F3000
30#define APUSYS_APU_PLL_SIZE 0x1000
31#define APUSYS_APU_ACC_BASE 0x190F4000
32#define APUSYS_APU_ACC_SIZE 0x1000
33
Edward-JW Yang9c783682021-06-28 11:08:10 +080034#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
35#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
developer2a56b2c2020-06-16 13:28:28 +080036#define SPM_BASE (IO_PHYS + 0x00006000)
Rex-BC Chen17903042021-08-10 11:10:58 +080037#define RGU_BASE (IO_PHYS + 0x00007000)
Edward-JW Yang9c783682021-06-28 11:08:10 +080038#define APMIXEDSYS (IO_PHYS + 0x0000C000)
Rex-BC Chen17903042021-08-10 11:10:58 +080039#define DRM_BASE (IO_PHYS + 0x0000D000)
Edward-JW Yang9c783682021-06-28 11:08:10 +080040#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
41#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
42#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
43#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
44#define VDOSYS0_BASE (IO_PHYS + 0x0C01A000)
45#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
developer0d3844d2021-07-09 16:55:51 +080046#define DVFSRC_BASE (IO_PHYS + 0x00012000)
developer8670d252021-03-19 22:13:11 +080047
48/*******************************************************************************
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080049 * DP/eDP related constants
50 ******************************************************************************/
developer479d1ad2022-07-12 10:24:26 +080051#define EDP_SEC_BASE (IO_PHYS + 0x0C504000)
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080052#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
developer479d1ad2022-07-12 10:24:26 +080053#define EDP_SEC_SIZE 0x1000
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080054#define DP_SEC_SIZE 0x1000
55
56/*******************************************************************************
developer912c7d22021-03-31 14:53:43 +080057 * GPIO related constants
58 ******************************************************************************/
59#define GPIO_BASE (IO_PHYS + 0x00005000)
60#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
61#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
62#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
63#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
64#define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000)
65#define IOCFG_TL_BASE (IO_PHYS + 0x01F40000)
66
67/*******************************************************************************
developer8670d252021-03-19 22:13:11 +080068 * UART related constants
69 ******************************************************************************/
70#define UART0_BASE (IO_PHYS + 0x01001100)
71#define UART1_BASE (IO_PHYS + 0x01001200)
72
73#define UART_BAUDRATE 115200
74
75/*******************************************************************************
developerddb7f402021-04-08 16:37:15 +080076 * PMIC related constants
77 ******************************************************************************/
78#define PMIC_WRAP_BASE (IO_PHYS + 0x00024000)
79
80/*******************************************************************************
developere2be2dd2021-08-19 15:34:43 +080081 * EMI MPU related constants
82 ******************************************************************************/
83#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
84#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000)
85
86/*******************************************************************************
developer8670d252021-03-19 22:13:11 +080087 * System counter frequency related constants
88 ******************************************************************************/
89#define SYS_COUNTER_FREQ_IN_TICKS 13000000
90#define SYS_COUNTER_FREQ_IN_MHZ 13
91
92/*******************************************************************************
christine.zhua22c10b2021-03-24 21:44:52 +080093 * GIC-600 & interrupt handling related constants
94 ******************************************************************************/
95/* Base MTK_platform compatible GIC memory map */
96#define BASE_GICD_BASE MT_GIC_BASE
97#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
98
developer8273a602021-03-25 11:26:46 +080099#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
100#define CIRQ_REG_NUM 23
101#define CIRQ_IRQ_NUM 730
102#define CIRQ_SPI_START 96
103#define MD_WDT_IRQ_BIT_ID 141
christine.zhua22c10b2021-03-24 21:44:52 +0800104/*******************************************************************************
developer8670d252021-03-19 22:13:11 +0800105 * Platform binary types for linking
106 ******************************************************************************/
107#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
108#define PLATFORM_LINKER_ARCH aarch64
109
110/*******************************************************************************
111 * Generic platform constants
112 ******************************************************************************/
113#define PLATFORM_STACK_SIZE 0x800
114
115#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
116
117#define PLAT_MAX_PWR_LVL U(3)
118#define PLAT_MAX_RET_STATE U(1)
119#define PLAT_MAX_OFF_STATE U(9)
120
121#define PLATFORM_SYSTEM_COUNT U(1)
122#define PLATFORM_MCUSYS_COUNT U(1)
123#define PLATFORM_CLUSTER_COUNT U(1)
124#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
125#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
126
127#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
128#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
129
130#define SOC_CHIP_ID U(0x8195)
131
132/*******************************************************************************
133 * Platform memory map related constants
134 ******************************************************************************/
135#define TZRAM_BASE 0x54600000
136#define TZRAM_SIZE 0x00030000
137
138/*******************************************************************************
139 * BL31 specific defines.
140 ******************************************************************************/
141/*
142 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
143 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
144 * little space for growth.
145 */
146#define BL31_BASE (TZRAM_BASE + 0x1000)
147#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
148
149/*******************************************************************************
150 * Platform specific page table and MMU setup constants
151 ******************************************************************************/
152#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
153#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
154#define MAX_XLAT_TABLES 16
155#define MAX_MMAP_REGIONS 16
156
157/*******************************************************************************
158 * Declarations and constants to access the mailboxes safely. Each mailbox is
159 * aligned on the biggest cache line size in the platform. This is known only
160 * to the platform as it might have a combination of integrated and external
161 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
162 * line at any cache level. They could belong to different cpus/clusters &
163 * get written while being protected by different locks causing corruption of
164 * a valid mailbox address.
165 ******************************************************************************/
166#define CACHE_WRITEBACK_SHIFT 6
167#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
168#endif /* PLATFORM_DEF_H */