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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaze3887a92019-01-30 20:29:50 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Dan Handleyed6ff952014-05-14 17:44:19 +01009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch.h>
Alexei Fedorovf41355c2019-09-13 14:11:59 +010012#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <arch_helpers.h>
14#include <bl1/bl1.h>
15#include <common/bl_common.h>
16#include <common/debug.h>
17#include <drivers/auth/auth_mod.h>
18#include <drivers/console.h>
19#include <lib/cpus/errata_report.h>
20#include <lib/utils.h>
21#include <plat/common/platform.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000022#include <smccc_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <tools_share/uuid.h>
24
Isla Mitchell99305012017-07-11 14:54:08 +010025#include "bl1_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010027/* BL1 Service UUID */
Roberto Vargaseace8f12018-04-26 13:36:53 +010028DEFINE_SVC_UUID2(bl1_svc_uid,
29 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75,
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010030 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
31
Yatharth Kochara65be2f2015-10-09 18:06:13 +010032static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010033
Sandrine Bailleux467d0572014-06-24 14:02:34 +010034/*******************************************************************************
Soby Mathew6e16a332018-01-10 12:51:34 +000035 * Helper utility to calculate the BL2 memory layout taking into consideration
36 * the BL1 RW data assuming that it is at the top of the memory layout.
Sandrine Bailleux467d0572014-06-24 14:02:34 +010037 ******************************************************************************/
Soby Mathew6e16a332018-01-10 12:51:34 +000038void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
39 meminfo_t *bl2_mem_layout)
Sandrine Bailleux467d0572014-06-24 14:02:34 +010040{
Sandrine Bailleux467d0572014-06-24 14:02:34 +010041 assert(bl1_mem_layout != NULL);
42 assert(bl2_mem_layout != NULL);
43
Yatharth Kochar51f76f62016-09-12 16:10:33 +010044 /*
45 * Remove BL1 RW data from the scope of memory visible to BL2.
46 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
47 */
48 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
49 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
50 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +010051
52 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
53}
Soby Mathew6e16a332018-01-10 12:51:34 +000054
Sandrine Bailleux467d0572014-06-24 14:02:34 +010055/*******************************************************************************
Antonio Nino Diaze3887a92019-01-30 20:29:50 +000056 * Setup function for BL1.
57 ******************************************************************************/
58void bl1_setup(void)
59{
60 /* Perform early platform-specific setup */
61 bl1_early_platform_setup();
62
Antonio Nino Diaze3887a92019-01-30 20:29:50 +000063 /* Perform late platform-specific setup */
64 bl1_plat_arch_setup();
Alexei Fedorovf41355c2019-09-13 14:11:59 +010065
66#if CTX_INCLUDE_PAUTH_REGS
67 /*
68 * Assert that the ARMv8.3-PAuth registers are present or an access
69 * fault will be triggered when they are being saved or restored.
70 */
71 assert(is_armv8_3_pauth_present());
72#endif /* CTX_INCLUDE_PAUTH_REGS */
Antonio Nino Diaze3887a92019-01-30 20:29:50 +000073}
74
75/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010076 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010077 * It also queries the platform to load and run next BL image. Only called
78 * by the primary cpu after a cold boot.
79 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010080void bl1_main(void)
81{
Yatharth Kochara65be2f2015-10-09 18:06:13 +010082 unsigned int image_id;
83
Dan Handley91b624e2014-07-29 17:14:00 +010084 /* Announce our arrival */
85 NOTICE(FIRMWARE_WELCOME_STR);
86 NOTICE("BL1: %s\n", version_string);
87 NOTICE("BL1: %s\n", build_message);
88
Yatharth Kochar5d361212016-06-28 17:07:09 +010089 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
90 (void *)BL1_RAM_LIMIT);
Dan Handley91b624e2014-07-29 17:14:00 +010091
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000092 print_errata_status();
Achin Gupta4f6ad662013-10-25 09:08:21 +010093
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +000094#if ENABLE_ASSERTIONS
Yatharth Kochar5d361212016-06-28 17:07:09 +010095 u_register_t val;
Achin Gupta4f6ad662013-10-25 09:08:21 +010096 /*
97 * Ensure that MMU/Caches and coherency are turned on
98 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -070099#ifdef __aarch64__
Dan Handley0cdebbd2015-03-30 17:15:16 +0100100 val = read_sctlr_el3();
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700101#else
102 val = read_sctlr();
Yatharth Kochar5d361212016-06-28 17:07:09 +0100103#endif
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100104 assert(val & SCTLR_M_BIT);
105 assert(val & SCTLR_C_BIT);
106 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100107 /*
108 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
109 * provided platform value
110 */
111 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
112 /*
113 * If CWG is zero, then no CWG information is available but we can
114 * at least check the platform value is less than the architectural
115 * maximum.
116 */
117 if (val != 0)
118 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
119 else
120 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000121#endif /* ENABLE_ASSERTIONS */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122
123 /* Perform remaining generic architectural setup from EL3 */
124 bl1_arch_setup();
125
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100126#if TRUSTED_BOARD_BOOT
127 /* Initialize authentication module */
128 auth_mod_init();
129#endif /* TRUSTED_BOARD_BOOT */
130
Achin Gupta4f6ad662013-10-25 09:08:21 +0100131 /* Perform platform setup in BL1. */
132 bl1_platform_setup();
133
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100134 /* Get the image id of next image to load and run. */
135 image_id = bl1_plat_get_next_image_id();
136
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100137 /*
138 * We currently interpret any image id other than
139 * BL2_IMAGE_ID as the start of firmware update.
140 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100141 if (image_id == BL2_IMAGE_ID)
142 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100143 else
144 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100145
146 bl1_prepare_next_image(image_id);
Antonio Nino Diaze3962d02017-02-16 16:17:19 +0000147
148 console_flush();
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100149}
150
151/*******************************************************************************
152 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
153 * Called by the primary cpu after a cold boot.
154 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
155 * loader etc.
156 ******************************************************************************/
Roberto Vargasbcfaeff2018-02-12 12:36:17 +0000157static void bl1_load_bl2(void)
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100158{
159 image_desc_t *image_desc;
160 image_info_t *image_info;
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100161 int err;
162
163 /* Get the image descriptor */
164 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
165 assert(image_desc);
166
167 /* Get the image info */
168 image_info = &image_desc->image_info;
Juan Castillo3a66aca2015-04-13 17:36:19 +0100169 INFO("BL1: Loading BL2\n");
170
Soby Mathew2f38ce32018-02-08 17:45:12 +0000171 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900172 if (err) {
173 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
174 plat_error_handler(err);
175 }
176
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100177 err = load_auth_image(BL2_IMAGE_ID, image_info);
Vikram Kanigirida567432014-04-15 18:08:08 +0100178 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100179 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100180 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100181 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000182
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900183 /* Allow platform to handle image information. */
Soby Mathew2f38ce32018-02-08 17:45:12 +0000184 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900185 if (err) {
186 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
187 plat_error_handler(err);
188 }
189
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100190 NOTICE("BL1: Booting BL2\n");
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191}
192
193/*******************************************************************************
Yatharth Kochar5d361212016-06-28 17:07:09 +0100194 * Function called just before handing over to the next BL to inform the user
195 * about the boot progress. In debug mode, also print details about the BL
196 * image's execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 ******************************************************************************/
Yatharth Kochar5d361212016-06-28 17:07:09 +0100198void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199{
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700200#ifdef __aarch64__
Juan Castillo7d199412015-12-14 09:35:25 +0000201 NOTICE("BL1: Booting BL31\n");
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700202#else
203 NOTICE("BL1: Booting BL32\n");
204#endif /* __aarch64__ */
Yatharth Kochar5d361212016-06-28 17:07:09 +0100205 print_entry_point_info(bl_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000207
208#if SPIN_ON_BL1_EXIT
209void print_debug_loop_message(void)
210{
211 NOTICE("BL1: Debug loop, spinning forever\n");
212 NOTICE("BL1: Please connect the debugger to continue\n");
213}
214#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100215
216/*******************************************************************************
217 * Top level handler for servicing BL1 SMCs.
218 ******************************************************************************/
219register_t bl1_smc_handler(unsigned int smc_fid,
220 register_t x1,
221 register_t x2,
222 register_t x3,
223 register_t x4,
224 void *cookie,
225 void *handle,
226 unsigned int flags)
227{
228
229#if TRUSTED_BOARD_BOOT
230 /*
231 * Dispatch FWU calls to FWU SMC handler and return its return
232 * value
233 */
234 if (is_fwu_fid(smc_fid)) {
235 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
236 handle, flags);
237 }
238#endif
239
240 switch (smc_fid) {
241 case BL1_SMC_CALL_COUNT:
242 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
243
244 case BL1_SMC_UID:
245 SMC_UUID_RET(handle, bl1_svc_uid);
246
247 case BL1_SMC_VERSION:
248 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
249
250 default:
251 break;
252 }
253
254 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
255 SMC_RET1(handle, SMC_UNK);
256}
dp-armcdd03cb2017-02-15 11:07:55 +0000257
258/*******************************************************************************
259 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
260 * compliance when invoking bl1_smc_handler.
261 ******************************************************************************/
262register_t bl1_smc_wrapper(uint32_t smc_fid,
263 void *cookie,
264 void *handle,
265 unsigned int flags)
266{
267 register_t x1, x2, x3, x4;
268
269 assert(handle);
270
271 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
272 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
273}