Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | .globl plat_get_my_entrypoint |
| 13 | .globl plat_secondary_cold_boot_setup |
| 14 | .globl plat_is_my_cpu_primary |
| 15 | .globl platform_mem_init |
| 16 | .globl plat_my_core_pos |
| 17 | .globl plat_fpga_calc_core_pos |
| 18 | .globl plat_crash_console_init |
| 19 | .globl plat_crash_console_putc |
| 20 | .globl plat_crash_console_flush |
| 21 | |
| 22 | /* ----------------------------------------------------------------------- |
Oliver Swede | 6e86c5a | 2019-12-02 13:21:52 +0000 | [diff] [blame] | 23 | * Indicate a cold boot for every CPU - warm boot is unsupported for the |
| 24 | * holding pen PSCI implementation. |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 25 | * ----------------------------------------------------------------------- |
| 26 | */ |
| 27 | func plat_get_my_entrypoint |
| 28 | mov x0, #0 |
| 29 | ret |
| 30 | endfunc plat_get_my_entrypoint |
| 31 | |
| 32 | /* ----------------------------------------------------------------------- |
| 33 | * void plat_secondary_cold_boot_setup (void); |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 34 | * ----------------------------------------------------------------------- |
| 35 | */ |
| 36 | func plat_secondary_cold_boot_setup |
Oliver Swede | 6e86c5a | 2019-12-02 13:21:52 +0000 | [diff] [blame] | 37 | /* |
| 38 | * Poll the CPU's hold entry until it indicates to jump |
| 39 | * to the entrypoint address. |
| 40 | */ |
| 41 | bl plat_my_core_pos |
| 42 | lsl x0, x0, #PLAT_FPGA_HOLD_ENTRY_SHIFT |
| 43 | ldr x1, =hold_base |
| 44 | ldr x2, =fpga_sec_entrypoint |
| 45 | poll_hold_entry: |
| 46 | ldr x3, [x1, x0] |
| 47 | cmp x3, #PLAT_FPGA_HOLD_STATE_GO |
| 48 | b.ne 1f |
| 49 | ldr x3, [x2] |
| 50 | br x3 |
| 51 | 1: |
| 52 | wfe |
| 53 | b poll_hold_entry |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 54 | endfunc plat_secondary_cold_boot_setup |
| 55 | |
| 56 | /* ----------------------------------------------------------------------- |
| 57 | * unsigned int plat_is_my_cpu_primary (void); |
| 58 | * |
| 59 | * Find out whether the current cpu is the primary cpu |
| 60 | * ----------------------------------------------------------------------- |
| 61 | */ |
| 62 | func plat_is_my_cpu_primary |
| 63 | mrs x0, mpidr_el1 |
| 64 | mov_imm x1, MPIDR_AFFINITY_MASK |
| 65 | and x0, x0, x1 |
| 66 | cmp x0, #FPGA_PRIMARY_CPU |
| 67 | cset w0, eq |
| 68 | ret |
| 69 | endfunc plat_is_my_cpu_primary |
| 70 | |
| 71 | func platform_mem_init |
| 72 | ret |
| 73 | endfunc platform_mem_init |
| 74 | |
| 75 | func plat_my_core_pos |
| 76 | mrs x0, mpidr_el1 |
| 77 | b plat_fpga_calc_core_pos |
| 78 | endfunc plat_my_core_pos |
| 79 | |
| 80 | /* ----------------------------------------------------------------------- |
| 81 | * unsigned int plat_fpga_calc_core_pos(u_register_t mpidr) |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 82 | * ----------------------------------------------------------------------- |
| 83 | */ |
| 84 | func plat_fpga_calc_core_pos |
Oliver Swede | 6e86c5a | 2019-12-02 13:21:52 +0000 | [diff] [blame] | 85 | /* |
| 86 | * Check for MT bit in MPIDR, which may be either value for images |
| 87 | * running on the FPGA. |
| 88 | * |
| 89 | * If not set, shift MPIDR to left to make it look as if in a |
| 90 | * multi-threaded implementation. |
| 91 | */ |
| 92 | tst x0, #MPIDR_MT_MASK |
| 93 | lsl x3, x0, #MPIDR_AFFINITY_BITS |
| 94 | csel x3, x3, x0, eq |
| 95 | |
| 96 | /* Extract individual affinity fields from MPIDR */ |
| 97 | ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS |
| 98 | ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS |
| 99 | ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS |
| 100 | |
| 101 | /* Compute linear position */ |
| 102 | mov x4, #FPGA_MAX_CPUS_PER_CLUSTER |
| 103 | madd x1, x2, x4, x1 |
| 104 | mov x5, #FPGA_MAX_PE_PER_CPU |
| 105 | madd x0, x1, x5, x0 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 106 | ret |
| 107 | endfunc plat_fpga_calc_core_pos |
| 108 | |
| 109 | func plat_crash_console_init |
| 110 | mov_imm x0, PLAT_FPGA_CRASH_UART_BASE |
| 111 | mov_imm x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ |
| 112 | mov_imm x2, PLAT_FPGA_CONSOLE_BAUDRATE |
| 113 | b console_pl011_core_init |
| 114 | endfunc plat_crash_console_init |
| 115 | |
| 116 | func plat_crash_console_putc |
| 117 | mov_imm x1, PLAT_FPGA_CRASH_UART_BASE |
| 118 | b console_pl011_core_putc |
| 119 | endfunc plat_crash_console_putc |
| 120 | |
| 121 | func plat_crash_console_flush |
| 122 | mov_imm x0, PLAT_FPGA_CRASH_UART_BASE |
| 123 | b console_pl011_core_flush |
| 124 | endfunc plat_crash_console_flush |