Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <denver.h> |
| 35 | #include <debug.h> |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 36 | #include <delay_timer.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 37 | #include <flowctrl.h> |
| 38 | #include <mmio.h> |
| 39 | #include <platform_def.h> |
| 40 | #include <pmc.h> |
| 41 | #include <psci.h> |
| 42 | #include <tegra_def.h> |
| 43 | #include <tegra_private.h> |
| 44 | |
| 45 | /* |
| 46 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 47 | * signals: CPU reset (3:0) and Core reset (19:16) |
| 48 | */ |
| 49 | #define CPU_CMPLX_RESET_CLR 0x344 |
| 50 | #define CPU_CORE_RESET_MASK 0x10001 |
| 51 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 52 | /* Clock and Reset controller registers for system clock's settings */ |
| 53 | #define SCLK_RATE 0x30 |
| 54 | #define SCLK_BURST_POLICY 0x28 |
| 55 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 56 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 57 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 58 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 59 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 60 | psci_power_state_t *req_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 61 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 62 | int pwr_lvl = psci_get_pstate_pwrlvl(power_state); |
| 63 | int state_id = psci_get_pstate_id(power_state); |
| 64 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
| 65 | |
| 66 | if (pwr_lvl > PLAT_MAX_PWR_LVL) |
| 67 | return PSCI_E_INVALID_PARAMS; |
| 68 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 69 | /* Sanity check the requested afflvl */ |
| 70 | if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { |
| 71 | /* |
| 72 | * It's possible to enter standby only on affinity level 0 i.e. |
| 73 | * a cpu on Tegra. Ignore any other affinity level. |
| 74 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 75 | if (pwr_lvl != MPIDR_AFFLVL0) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 76 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 77 | |
| 78 | /* power domain in standby state */ |
| 79 | req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; |
| 80 | |
| 81 | return PSCI_E_SUCCESS; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 82 | } |
| 83 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 84 | /* |
| 85 | * Sanity check the requested state id, power level and CPU number. |
| 86 | * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU |
| 87 | * i.e. CPU 0 |
| 88 | */ |
| 89 | if ((pwr_lvl != PLAT_MAX_PWR_LVL) || |
| 90 | (state_id != PSTATE_ID_SOC_POWERDN) || |
| 91 | (cpu != 0)) { |
| 92 | ERROR("unsupported state id @ power level\n"); |
| 93 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 94 | } |
| 95 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 96 | /* Set lower power states to PLAT_MAX_OFF_STATE */ |
| 97 | for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
| 98 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 99 | |
| 100 | /* Set the SYSTEM_SUSPEND state-id */ |
| 101 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 102 | PSTATE_ID_SOC_POWERDN; |
| 103 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 104 | return PSCI_E_SUCCESS; |
| 105 | } |
| 106 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 107 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 108 | { |
| 109 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 110 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 111 | |
| 112 | if (cpu_powergate_mask[cpu] == 0) { |
| 113 | |
| 114 | /* Deassert CPU reset signals */ |
| 115 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
| 116 | |
| 117 | /* Power on CPU using PMC */ |
| 118 | tegra_pmc_cpu_on(cpu); |
| 119 | |
| 120 | /* Fill in the CPU powergate mask */ |
| 121 | cpu_powergate_mask[cpu] = 1; |
| 122 | |
| 123 | } else { |
| 124 | /* Power on CPU using Flow Controller */ |
| 125 | tegra_fc_cpu_on(cpu); |
| 126 | } |
| 127 | |
| 128 | return PSCI_E_SUCCESS; |
| 129 | } |
| 130 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 131 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 132 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 133 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 134 | return PSCI_E_SUCCESS; |
| 135 | } |
| 136 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 137 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 138 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 139 | #if DEBUG |
| 140 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 141 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 142 | /* SYSTEM_SUSPEND only on CPU0 */ |
| 143 | assert(cpu == 0); |
| 144 | #endif |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 145 | |
| 146 | /* Allow restarting CPU #1 using PMC on suspend exit */ |
| 147 | cpu_powergate_mask[1] = 0; |
| 148 | |
| 149 | /* Program FC to enter suspend state */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 150 | tegra_fc_cpu_powerdn(read_mpidr()); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 151 | |
| 152 | /* Suspend DCO operations */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 153 | write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 154 | |
| 155 | return PSCI_E_SUCCESS; |
| 156 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 157 | |
| 158 | int tegra_soc_prepare_system_reset(void) |
| 159 | { |
| 160 | /* |
| 161 | * Set System Clock (SCLK) to POR default so that the clock source |
| 162 | * for the PMC APB clock would not be changed due to system reset. |
| 163 | */ |
| 164 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
| 165 | SCLK_BURST_POLICY_DEFAULT); |
| 166 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 167 | |
| 168 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 169 | mdelay(1); |
| 170 | |
| 171 | return PSCI_E_SUCCESS; |
| 172 | } |