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Achin Gupta375f5382014-02-18 18:12:48 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta375f5382014-02-18 18:12:48 +000031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
Achin Gupta375f5382014-02-18 18:12:48 +000033#include <bl_common.h>
Achin Gupta375f5382014-02-18 18:12:48 +000034#include <context_mgmt.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010036#include "tspd_private.h"
Achin Gupta375f5382014-02-18 18:12:48 +000037
38/*******************************************************************************
39 * Given a secure payload entrypoint, register width, cpu id & pointer to a
40 * context data structure, this function will create a secure context ready for
41 * programming an entry into the secure payload.
42 ******************************************************************************/
43int32_t tspd_init_secure_context(uint64_t entrypoint,
Achin Guptaaeaab682014-05-09 13:21:31 +010044 uint32_t rw,
45 uint64_t mpidr,
46 tsp_context_t *tsp_ctx)
Achin Gupta375f5382014-02-18 18:12:48 +000047{
Andrew Thoelke4e126072014-06-04 21:10:52 +010048 entry_point_info_t ep;
49 uint32_t ep_attr;
Achin Gupta375f5382014-02-18 18:12:48 +000050
51 /* Passing a NULL context is a critical programming error */
52 assert(tsp_ctx);
53
54 /*
55 * We support AArch64 TSP for now.
56 * TODO: Add support for AArch32 TSP
57 */
58 assert(rw == TSP_AARCH64);
59
Andrew Thoelke4e126072014-06-04 21:10:52 +010060 /* Associate this context with the cpu specified */
61 tsp_ctx->mpidr = mpidr;
62 tsp_ctx->state = 0;
Achin Gupta18d6eaf2014-05-04 18:23:26 +010063 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF);
Achin Gupta18d6eaf2014-05-04 18:23:26 +010064 clr_std_smc_active_flag(tsp_ctx->state);
Achin Gupta375f5382014-02-18 18:12:48 +000065
Andrew Thoelke4e126072014-06-04 21:10:52 +010066 cm_set_context_by_mpidr(mpidr, &tsp_ctx->cpu_ctx, SECURE);
67
68 /* initialise an entrypoint to set up the CPU context */
69 ep_attr = SECURE | EP_ST_ENABLE;
70 if (read_sctlr_el3() & SCTLR_EE_BIT)
71 ep_attr |= EP_EE_BIG;
72 SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, ep_attr);
73 ep.pc = entrypoint;
74 ep.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
75 memset(&ep.args, 0, sizeof(ep.args));
Achin Gupta375f5382014-02-18 18:12:48 +000076
Andrew Thoelke4e126072014-06-04 21:10:52 +010077 cm_init_context(mpidr, &ep);
Achin Gupta375f5382014-02-18 18:12:48 +000078
Achin Gupta375f5382014-02-18 18:12:48 +000079 return 0;
80}
81
82/*******************************************************************************
83 * This function takes an SP context pointer and:
84 * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx.
85 * 2. Saves the current C runtime state (callee saved registers) on the stack
86 * frame and saves a reference to this state.
87 * 3. Calls el3_exit() so that the EL3 system and general purpose registers
88 * from the tsp_ctx->cpu_ctx are used to enter the secure payload image.
89 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010090uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx)
Achin Gupta375f5382014-02-18 18:12:48 +000091{
92 uint64_t rc;
93
Juan Castillof558cac2014-06-05 09:45:36 +010094 assert(tsp_ctx != NULL);
Achin Gupta375f5382014-02-18 18:12:48 +000095 assert(tsp_ctx->c_rt_ctx == 0);
96
97 /* Apply the Secure EL1 system register context and switch to it */
Andrew Thoelkea2f65532014-05-14 17:09:32 +010098 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
Achin Gupta375f5382014-02-18 18:12:48 +000099 cm_el1_sysregs_context_restore(SECURE);
100 cm_set_next_eret_context(SECURE);
101
102 rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx);
103#if DEBUG
104 tsp_ctx->c_rt_ctx = 0;
105#endif
106
107 return rc;
108}
109
110
111/*******************************************************************************
112 * This function takes an SP context pointer and:
113 * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx.
114 * 2. Restores the current C runtime state (callee saved registers) from the
115 * stack frame using the reference to this state saved in tspd_enter_sp().
116 * 3. It does not need to save any general purpose or EL3 system register state
117 * as the generic smc entry routine should have saved those.
118 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100119void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret)
Achin Gupta375f5382014-02-18 18:12:48 +0000120{
Juan Castillof558cac2014-06-05 09:45:36 +0100121 assert(tsp_ctx != NULL);
Achin Gupta375f5382014-02-18 18:12:48 +0000122 /* Save the Secure EL1 system register context */
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100123 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
Achin Gupta375f5382014-02-18 18:12:48 +0000124 cm_el1_sysregs_context_save(SECURE);
125
126 assert(tsp_ctx->c_rt_ctx != 0);
127 tspd_exit_sp(tsp_ctx->c_rt_ctx, ret);
128
129 /* Should never reach here */
130 assert(0);
131}