| Jiafei Pan | 19ccc51 | 2021-09-13 16:12:28 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018-2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLAT_DEF_H |
| 8 | #define PLAT_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <cortex_a72.h> |
| 12 | /* |
| 13 | * Required without TBBR. |
| 14 | * To include the defines for DDR PHY |
| 15 | * Images. |
| 16 | */ |
| 17 | #include <tbbr_img_def.h> |
| 18 | |
| 19 | #include <policy.h> |
| 20 | #include <soc.h> |
| 21 | |
| 22 | |
| 23 | #define NXP_SYSCLK_FREQ 100000000 |
| 24 | #define NXP_DDRCLK_FREQ 100000000 |
| 25 | |
| 26 | /* UART related definition */ |
| 27 | #define NXP_CONSOLE_ADDR NXP_UART_ADDR |
| 28 | #define NXP_CONSOLE_BAUDRATE 115200 |
| 29 | |
| 30 | #define NXP_SPD_EEPROM0 0x51 |
| 31 | |
| 32 | /* Size of cacheable stacks */ |
| 33 | #if defined(IMAGE_BL2) |
| 34 | #if defined(TRUSTED_BOARD_BOOT) |
| 35 | #define PLATFORM_STACK_SIZE 0x2000 |
| 36 | #else |
| 37 | #define PLATFORM_STACK_SIZE 0x1000 |
| 38 | #endif |
| 39 | #elif defined(IMAGE_BL31) |
| 40 | #define PLATFORM_STACK_SIZE 0x1000 |
| 41 | #endif |
| 42 | |
| 43 | /* SD block buffer */ |
| 44 | #define NXP_SD_BLOCK_BUF_SIZE (0xC000) |
| 45 | |
| 46 | #ifdef SD_BOOT |
| 47 | #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ |
| 48 | - NXP_SD_BLOCK_BUF_SIZE) |
| 49 | #else |
| 50 | #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) |
| 51 | #endif |
| 52 | #define BL2_TEXT_LIMIT (BL2_LIMIT) |
| 53 | |
| 54 | /* IO defines as needed by IO driver framework */ |
| 55 | #define MAX_IO_DEVICES 4 |
| 56 | #define MAX_IO_BLOCK_DEVICES 1 |
| 57 | #define MAX_IO_HANDLES 4 |
| 58 | |
| 59 | #define BL31_WDOG_SEC 89 |
| 60 | |
| 61 | /* |
| 62 | * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 63 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 64 | * as Group 0 interrupts. |
| 65 | */ |
| 66 | #define PLAT_LS_G1S_IRQ_PROPS(grp) \ |
| 67 | INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 68 | GIC_INTR_CFG_EDGE) |
| 69 | |
| 70 | /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ |
| 71 | #define PLAT_LS_G0_IRQ_PROPS(grp) \ |
| 72 | INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 73 | GIC_INTR_CFG_EDGE), \ |
| 74 | INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 75 | GIC_INTR_CFG_LEVEL) |
| 76 | #endif /* PLAT_DEF_H */ |