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git01.mediatek.com / filogic / atf / 2ea0584e81d9a64583f0da98ea752a613a332248 / . / plat / arm / board / tc / fdts / tc_spmc_manifest.dtsi
blob: 3bc0cbb434f64ab3bbbf821d788c88fc2916a410 [file] [log] [blame]
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]1/*
Boyan Karatotev8dec1f52023-12-20 16:28:23 +0000[diff] [blame]2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Boyan Karatotev88309be2023-12-04 16:12:08 +0000[diff] [blame]6#include <platform_def.h>
7
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]8/ {
9 compatible = "arm,ffa-core-manifest-1.0";
10 #address-cells = <2>;
J-Alves92928182023-03-16 15:26:52 +0000[diff] [blame]11 #size-cells = <2>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]12
13 attribute {
14 spmc_id = <0x8000>;
15 maj_ver = <0x1>;
Kathleen Capellafa435ea2023-09-05 14:33:29 -0400[diff] [blame]16 min_ver = <0x2>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]17 exec_state = <0x0>;
18 load_address = <0x0 0xfd000000>;
19 entrypoint = <0x0 0xfd000000>;
20 binary_size = <0x80000>;
21 };
22
Boyan Karatotev8dec1f52023-12-20 16:28:23 +0000[diff] [blame]23 hafnium:hypervisor {
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]24 compatible = "hafnium,hafnium";
Boyan Karatotev8dec1f52023-12-20 16:28:23 +0000[diff] [blame]25 /* filled in in top level .dts */
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]26 };
27
28 cpus {
29 #address-cells = <0x2>;
30 #size-cells = <0x0>;
31
32 CPU0:cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,armv8";
35 reg = <0x0 0x0>;
36 enable-method = "psci";
37 };
38
39 /*
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]40 * SPMC (Hafnium) requires secondary cpu nodes are declared in
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]41 * descending order
42 */
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]43 CPU7:cpu@700 {
44 device_type = "cpu";
45 compatible = "arm,armv8";
46 reg = <0x0 0x700>;
47 enable-method = "psci";
48 };
49
50 CPU6:cpu@600 {
51 device_type = "cpu";
52 compatible = "arm,armv8";
53 reg = <0x0 0x600>;
54 enable-method = "psci";
55 };
56
57 CPU5:cpu@500 {
58 device_type = "cpu";
59 compatible = "arm,armv8";
60 reg = <0x0 0x500>;
61 enable-method = "psci";
62 };
63
64 CPU4:cpu@400 {
65 device_type = "cpu";
66 compatible = "arm,armv8";
67 reg = <0x0 0x400>;
68 enable-method = "psci";
69 };
70
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]71 CPU3:cpu@300 {
72 device_type = "cpu";
73 compatible = "arm,armv8";
74 reg = <0x0 0x300>;
75 enable-method = "psci";
76 };
77
78 CPU2:cpu@200 {
79 device_type = "cpu";
80 compatible = "arm,armv8";
81 reg = <0x0 0x200>;
82 enable-method = "psci";
83 };
84
85 CPU1:cpu@100 {
86 device_type = "cpu";
87 compatible = "arm,armv8";
88 reg = <0x0 0x100>;
89 enable-method = "psci";
90 };
91 };
92
Boyan Karatotev88309be2023-12-04 16:12:08 +0000[diff] [blame]93 /* the full secure world range */
J-Alves92928182023-03-16 15:26:52 +0000[diff] [blame]94 memory@0 {
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]95 device_type = "memory";
Boyan Karatotev88309be2023-12-04 16:12:08 +0000[diff] [blame]96 reg = <0x0 TC_TZC_DRAM1_BASE 0x0 TC_TZC_DRAM1_SIZE>,
J-Alves92928182023-03-16 15:26:52 +0000[diff] [blame]97 <0x0 0xff000000 0x0 0x1000000>;
98 };
99
100 memory@1 {
101 device_type = "ns-memory";
Tudor Cretu77b301a2021-09-24 12:09:53 +0000[diff] [blame]102 reg =
103#ifdef TS_SP_FW_CONFIG
104 <0x0 0x08000000 0x0 0x4000000>,
105#endif /* TS_SP_FW_CONFIG */
Boyan Karatotev88309be2023-12-04 16:12:08 +0000[diff] [blame]106 <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
107 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
108 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]109 };
110};