Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 1 | /* |
Harvey Hsieh | b9b374f | 2016-11-15 22:04:51 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 9 | #include <bl_common.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 10 | #include <debug.h> |
| 11 | #include <mce.h> |
| 12 | #include <memctrl.h> |
| 13 | #include <memctrl_v2.h> |
| 14 | #include <mmio.h> |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 15 | #include <smmu.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 16 | #include <string.h> |
| 17 | #include <tegra_def.h> |
Varun Wadekar | e81177d | 2016-07-18 17:43:41 -0700 | [diff] [blame] | 18 | #include <tegra_platform.h> |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 19 | #include <utils.h> |
| 20 | #include <xlat_tables_v2.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 21 | |
| 22 | /* Video Memory base and size (live values) */ |
| 23 | static uint64_t video_mem_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 24 | static uint64_t video_mem_size_mb; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 25 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 26 | static void tegra_memctrl_reconfig_mss_clients(void) |
| 27 | { |
| 28 | #if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS |
| 29 | uint32_t val, wdata_0, wdata_1; |
| 30 | |
| 31 | /* |
| 32 | * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for |
| 33 | * boot and strongly ordered MSS clients to flush existing memory |
| 34 | * traffic and stall future requests. |
| 35 | */ |
| 36 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); |
| 37 | assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL); |
| 38 | |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 39 | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB | |
| 40 | #if ENABLE_AFI_DEVICE |
| 41 | MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB | |
| 42 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 43 | MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | |
| 44 | MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | |
| 45 | MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB; |
| 46 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |
| 47 | |
| 48 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 49 | do { |
| 50 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 51 | } while ((val & wdata_0) != wdata_0); |
| 52 | |
| 53 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 54 | do { |
| 55 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 56 | } while ((val & wdata_0) != wdata_0); |
| 57 | |
| 58 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); |
| 59 | assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL); |
| 60 | |
| 61 | wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | |
| 62 | MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | |
| 63 | MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | |
| 64 | MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | |
| 65 | MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | |
| 66 | MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | |
| 67 | MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | |
| 68 | MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | |
| 69 | MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | |
| 70 | MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB; |
| 71 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); |
| 72 | |
| 73 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 74 | do { |
| 75 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 76 | } while ((val & wdata_1) != wdata_1); |
| 77 | |
| 78 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 79 | do { |
| 80 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 81 | } while ((val & wdata_1) != wdata_1); |
| 82 | |
| 83 | /* |
| 84 | * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and |
| 85 | * strongly ordered MSS clients. ROC needs to be single point |
| 86 | * of control on overriding the memory type. So, remove TSA's |
| 87 | * memtype override. |
| 88 | */ |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 89 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 90 | mc_set_tsa_passthrough(AFIW); |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 91 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 92 | mc_set_tsa_passthrough(HDAW); |
| 93 | mc_set_tsa_passthrough(SATAW); |
| 94 | mc_set_tsa_passthrough(XUSB_HOSTW); |
| 95 | mc_set_tsa_passthrough(XUSB_DEVW); |
| 96 | mc_set_tsa_passthrough(SDMMCWAB); |
| 97 | mc_set_tsa_passthrough(APEDMAW); |
| 98 | mc_set_tsa_passthrough(SESWR); |
| 99 | mc_set_tsa_passthrough(ETRW); |
| 100 | mc_set_tsa_passthrough(AXISW); |
| 101 | mc_set_tsa_passthrough(EQOSW); |
| 102 | mc_set_tsa_passthrough(UFSHCW); |
| 103 | mc_set_tsa_passthrough(BPMPDMAW); |
| 104 | mc_set_tsa_passthrough(AONDMAW); |
| 105 | mc_set_tsa_passthrough(SCEDMAW); |
| 106 | |
| 107 | /* |
| 108 | * Change COH_PATH_OVERRIDE_SO_DEV from NO_OVERRIDE -> FORCE_COHERENT |
| 109 | * for boot and strongly ordered MSS clients. This steers all sodev |
| 110 | * transactions to ROC. |
| 111 | * |
| 112 | * Change AXID_OVERRIDE/AXID_OVERRIDE_SO_DEV only for some clients |
| 113 | * whose AXI IDs we know and trust. |
| 114 | */ |
| 115 | |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 116 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 117 | /* Match AFIW */ |
| 118 | mc_set_forced_coherent_so_dev_cfg(AFIR); |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 119 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 120 | |
| 121 | /* |
| 122 | * See bug 200131110 comment #35 - there are no normal requests |
| 123 | * and AWID for SO/DEV requests is hardcoded in RTL for a |
| 124 | * particular PCIE controller |
| 125 | */ |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 126 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 127 | mc_set_forced_coherent_so_dev_cfg(AFIW); |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 128 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 129 | mc_set_forced_coherent_cfg(HDAR); |
| 130 | mc_set_forced_coherent_cfg(HDAW); |
| 131 | mc_set_forced_coherent_cfg(SATAR); |
| 132 | mc_set_forced_coherent_cfg(SATAW); |
| 133 | mc_set_forced_coherent_cfg(XUSB_HOSTR); |
| 134 | mc_set_forced_coherent_cfg(XUSB_HOSTW); |
| 135 | mc_set_forced_coherent_cfg(XUSB_DEVR); |
| 136 | mc_set_forced_coherent_cfg(XUSB_DEVW); |
| 137 | mc_set_forced_coherent_cfg(SDMMCRAB); |
| 138 | mc_set_forced_coherent_cfg(SDMMCWAB); |
| 139 | |
| 140 | /* Match APEDMAW */ |
| 141 | mc_set_forced_coherent_axid_so_dev_cfg(APEDMAR); |
| 142 | |
| 143 | /* |
| 144 | * See bug 200131110 comment #35 - AWID for normal requests |
| 145 | * is 0x80 and AWID for SO/DEV requests is 0x01 |
| 146 | */ |
| 147 | mc_set_forced_coherent_axid_so_dev_cfg(APEDMAW); |
| 148 | mc_set_forced_coherent_cfg(SESRD); |
| 149 | mc_set_forced_coherent_cfg(SESWR); |
| 150 | mc_set_forced_coherent_cfg(ETRR); |
| 151 | mc_set_forced_coherent_cfg(ETRW); |
| 152 | mc_set_forced_coherent_cfg(AXISR); |
| 153 | mc_set_forced_coherent_cfg(AXISW); |
| 154 | mc_set_forced_coherent_cfg(EQOSR); |
| 155 | mc_set_forced_coherent_cfg(EQOSW); |
| 156 | mc_set_forced_coherent_cfg(UFSHCR); |
| 157 | mc_set_forced_coherent_cfg(UFSHCW); |
| 158 | mc_set_forced_coherent_cfg(BPMPDMAR); |
| 159 | mc_set_forced_coherent_cfg(BPMPDMAW); |
| 160 | mc_set_forced_coherent_cfg(AONDMAR); |
| 161 | mc_set_forced_coherent_cfg(AONDMAW); |
| 162 | mc_set_forced_coherent_cfg(SCEDMAR); |
| 163 | mc_set_forced_coherent_cfg(SCEDMAW); |
| 164 | |
| 165 | /* |
| 166 | * At this point, ordering can occur at ROC. So, remove PCFIFO's |
| 167 | * control over ordering requests. |
| 168 | * |
| 169 | * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for |
| 170 | * boot and strongly ordered MSS clients |
| 171 | */ |
| 172 | val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL & |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 173 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 174 | mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) & |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 175 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 176 | mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) & |
| 177 | mc_set_pcfifo_unordered_boot_so_mss(1, SATAW); |
| 178 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val); |
| 179 | |
| 180 | val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & |
| 181 | mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & |
| 182 | mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW); |
| 183 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val); |
| 184 | |
| 185 | val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & |
| 186 | mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB); |
| 187 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val); |
| 188 | |
| 189 | val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & |
| 190 | mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & |
| 191 | mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & |
| 192 | mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & |
| 193 | mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW) & |
| 194 | mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & |
| 195 | mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & |
| 196 | mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & |
| 197 | mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); |
| 198 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val); |
| 199 | |
| 200 | val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & |
| 201 | mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW); |
| 202 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val); |
| 203 | |
| 204 | /* |
| 205 | * At this point, ordering can occur at ROC. SMMU need not |
| 206 | * reorder any requests. |
| 207 | * |
| 208 | * Change SMMU_*_ORDERED_CLIENT from ORDERED -> UNORDERED |
| 209 | * for boot and strongly ordered MSS clients |
| 210 | */ |
| 211 | val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL & |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 212 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 213 | mc_set_smmu_unordered_boot_so_mss(1, AFIW) & |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 214 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 215 | mc_set_smmu_unordered_boot_so_mss(1, HDAW) & |
| 216 | mc_set_smmu_unordered_boot_so_mss(1, SATAW); |
| 217 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val); |
| 218 | |
| 219 | val = MC_SMMU_CLIENT_CONFIG2_RESET_VAL & |
| 220 | mc_set_smmu_unordered_boot_so_mss(2, XUSB_HOSTW) & |
| 221 | mc_set_smmu_unordered_boot_so_mss(2, XUSB_DEVW); |
| 222 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG2, val); |
| 223 | |
| 224 | val = MC_SMMU_CLIENT_CONFIG3_RESET_VAL & |
| 225 | mc_set_smmu_unordered_boot_so_mss(3, SDMMCWAB); |
| 226 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG3, val); |
| 227 | |
| 228 | val = MC_SMMU_CLIENT_CONFIG4_RESET_VAL & |
| 229 | mc_set_smmu_unordered_boot_so_mss(4, SESWR) & |
| 230 | mc_set_smmu_unordered_boot_so_mss(4, ETRW) & |
| 231 | mc_set_smmu_unordered_boot_so_mss(4, AXISW) & |
| 232 | mc_set_smmu_unordered_boot_so_mss(4, EQOSW) & |
| 233 | mc_set_smmu_unordered_boot_so_mss(4, UFSHCW) & |
| 234 | mc_set_smmu_unordered_boot_so_mss(4, BPMPDMAW) & |
| 235 | mc_set_smmu_unordered_boot_so_mss(4, AONDMAW) & |
| 236 | mc_set_smmu_unordered_boot_so_mss(4, SCEDMAW); |
| 237 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG4, val); |
| 238 | |
| 239 | val = MC_SMMU_CLIENT_CONFIG5_RESET_VAL & |
| 240 | mc_set_smmu_unordered_boot_so_mss(5, APEDMAW); |
| 241 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG5, val); |
| 242 | |
| 243 | /* |
| 244 | * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS |
| 245 | * clients to allow memory traffic from all clients to start passing |
| 246 | * through ROC |
| 247 | */ |
| 248 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); |
| 249 | assert(val == wdata_0); |
| 250 | |
| 251 | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; |
| 252 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |
| 253 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 254 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); |
| 255 | assert(val == wdata_1); |
| 256 | |
| 257 | wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; |
| 258 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); |
| 259 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 260 | #endif |
| 261 | } |
| 262 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 263 | static void tegra_memctrl_set_overrides(void) |
| 264 | { |
| 265 | tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
| 266 | const mc_txn_override_cfg_t *mc_txn_override_cfgs; |
| 267 | uint32_t num_txn_override_cfgs; |
| 268 | uint32_t i, val; |
| 269 | |
| 270 | /* Get the settings from the platform */ |
| 271 | assert(plat_mc_settings); |
| 272 | mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg; |
| 273 | num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs; |
| 274 | |
| 275 | /* |
| 276 | * Set the MC_TXN_OVERRIDE registers for write clients. |
| 277 | */ |
| 278 | if ((tegra_chipid_is_t186()) && |
| 279 | (!tegra_platform_is_silicon() || |
| 280 | (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) { |
| 281 | |
| 282 | /* |
| 283 | * GPU and NVENC settings for Tegra186 simulation and |
| 284 | * Silicon rev. A01 |
| 285 | */ |
| 286 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR); |
| 287 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 288 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR, |
| 289 | val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); |
| 290 | |
| 291 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2); |
| 292 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 293 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2, |
| 294 | val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); |
| 295 | |
| 296 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR); |
| 297 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 298 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR, |
| 299 | val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID); |
| 300 | |
| 301 | } else { |
| 302 | |
| 303 | /* |
| 304 | * Settings for Tegra186 silicon rev. A02 and onwards. |
| 305 | */ |
| 306 | for (i = 0; i < num_txn_override_cfgs; i++) { |
| 307 | val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset); |
| 308 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 309 | tegra_mc_write_32(mc_txn_override_cfgs[i].offset, |
| 310 | val | mc_txn_override_cfgs[i].cgid_tag); |
| 311 | } |
| 312 | } |
| 313 | } |
| 314 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 315 | /* |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 316 | * Init Memory controller during boot. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 317 | */ |
| 318 | void tegra_memctrl_setup(void) |
| 319 | { |
| 320 | uint32_t val; |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 321 | const uint32_t *mc_streamid_override_regs; |
| 322 | uint32_t num_streamid_override_regs; |
| 323 | const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs; |
| 324 | uint32_t num_streamid_sec_cfgs; |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 325 | tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 326 | uint32_t i; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 327 | |
| 328 | INFO("Tegra Memory Controller (v2)\n"); |
| 329 | |
Varun Wadekar | 6cb25f9 | 2016-12-19 11:17:54 -0800 | [diff] [blame] | 330 | #if ENABLE_SMMU_DEVICE |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 331 | /* Program the SMMU pagesize */ |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 332 | tegra_smmu_init(); |
Varun Wadekar | 6cb25f9 | 2016-12-19 11:17:54 -0800 | [diff] [blame] | 333 | #endif |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 334 | /* Get the settings from the platform */ |
| 335 | assert(plat_mc_settings); |
| 336 | mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg; |
| 337 | num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs; |
| 338 | mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg; |
| 339 | num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 340 | |
| 341 | /* Program all the Stream ID overrides */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 342 | for (i = 0; i < num_streamid_override_regs; i++) |
| 343 | tegra_mc_streamid_write_32(mc_streamid_override_regs[i], |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 344 | MC_STREAM_ID_MAX); |
| 345 | |
| 346 | /* Program the security config settings for all Stream IDs */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 347 | for (i = 0; i < num_streamid_sec_cfgs; i++) { |
| 348 | val = mc_streamid_sec_cfgs[i].override_enable << 16 | |
| 349 | mc_streamid_sec_cfgs[i].override_client_inputs << 8 | |
| 350 | mc_streamid_sec_cfgs[i].override_client_ns_flag << 0; |
| 351 | tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | /* |
| 355 | * All requests at boot time, and certain requests during |
| 356 | * normal run time, are physically addressed and must bypass |
| 357 | * the SMMU. The client hub logic implements a hardware bypass |
| 358 | * path around the Translation Buffer Units (TBU). During |
| 359 | * boot-time, the SMMU_BYPASS_CTRL register (which defaults to |
| 360 | * TBU_BYPASS mode) will be used to steer all requests around |
| 361 | * the uninitialized TBUs. During normal operation, this register |
| 362 | * is locked into TBU_BYPASS_SID config, which routes requests |
| 363 | * with special StreamID 0x7f on the bypass path and all others |
| 364 | * through the selected TBU. This is done to disable SMMU Bypass |
| 365 | * mode, as it could be used to circumvent SMMU security checks. |
| 366 | */ |
| 367 | tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 368 | MC_SMMU_BYPASS_CONFIG_SETTINGS); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 369 | |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 370 | /* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 371 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 372 | * Memory Controller traffic. This is needed as the Memory Controller |
| 373 | * boots with MSS having all control, but ROC provides a performance |
| 374 | * boost as compared to MSS. |
| 375 | */ |
| 376 | tegra_memctrl_reconfig_mss_clients(); |
| 377 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 378 | /* Program overrides for MC transactions */ |
| 379 | tegra_memctrl_set_overrides(); |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 380 | } |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 381 | |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 382 | /* |
| 383 | * Restore Memory Controller settings after "System Suspend" |
| 384 | */ |
| 385 | void tegra_memctrl_restore_settings(void) |
| 386 | { |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 387 | /* |
| 388 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 389 | * Memory Controller traffic. This is needed as the Memory Controller |
| 390 | * resets during System Suspend with MSS having all control, but ROC |
| 391 | * provides a performance boost as compared to MSS. |
| 392 | */ |
| 393 | tegra_memctrl_reconfig_mss_clients(); |
| 394 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 395 | /* Program overrides for MC transactions */ |
| 396 | tegra_memctrl_set_overrides(); |
| 397 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 398 | /* video memory carveout region */ |
| 399 | if (video_mem_base) { |
| 400 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, |
| 401 | (uint32_t)video_mem_base); |
| 402 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 403 | (uint32_t)(video_mem_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 404 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 405 | |
| 406 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 407 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 408 | * CCPLEX. |
| 409 | */ |
| 410 | mce_update_gsc_videomem(); |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | /* |
| 415 | * Secure the BL31 DRAM aperture. |
| 416 | * |
| 417 | * phys_base = physical base of TZDRAM aperture |
| 418 | * size_in_bytes = size of aperture in bytes |
| 419 | */ |
| 420 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 421 | { |
| 422 | /* |
| 423 | * Setup the Memory controller to allow only secure accesses to |
| 424 | * the TZDRAM carveout |
| 425 | */ |
| 426 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 427 | |
| 428 | tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); |
| 429 | tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); |
| 430 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 431 | |
| 432 | /* |
Harvey Hsieh | c95802d | 2016-07-29 20:10:59 +0800 | [diff] [blame] | 433 | * When TZ encryption enabled, |
| 434 | * We need setup TZDRAM before CPU to access TZ Carveout, |
| 435 | * otherwise CPU will fetch non-decrypted data. |
| 436 | * So save TZDRAM setting for retore by SC7 resume FW. |
| 437 | */ |
| 438 | |
| 439 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, |
| 440 | tegra_mc_read_32(MC_SECURITY_CFG0_0)); |
| 441 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, |
| 442 | tegra_mc_read_32(MC_SECURITY_CFG3_0)); |
| 443 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI, |
| 444 | tegra_mc_read_32(MC_SECURITY_CFG1_0)); |
| 445 | |
| 446 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 447 | * MCE propagates the security configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 448 | * CCPLEX. |
| 449 | */ |
| 450 | mce_update_gsc_tzdram(); |
| 451 | } |
| 452 | |
| 453 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 454 | * Secure the BL31 TZRAM aperture. |
| 455 | * |
| 456 | * phys_base = physical base of TZRAM aperture |
| 457 | * size_in_bytes = size of aperture in bytes |
| 458 | */ |
| 459 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 460 | { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 461 | uint32_t index; |
| 462 | uint32_t total_128kb_blocks = size_in_bytes >> 17; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 463 | uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 464 | uint32_t val; |
| 465 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 466 | INFO("Configuring TrustZone SRAM Memory Carveout\n"); |
| 467 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 468 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 469 | * Reset the access configuration registers to restrict access |
| 470 | * to the TZRAM aperture |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 471 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 472 | for (index = MC_TZRAM_CLIENT_ACCESS_CFG0; |
| 473 | index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 474 | index += 4U) { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 475 | tegra_mc_write_32(index, 0); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 476 | } |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 477 | |
| 478 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 479 | * Set the TZRAM base. TZRAM base must be 4k aligned, at least. |
| 480 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 481 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 482 | tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); |
| 483 | tegra_mc_write_32(MC_TZRAM_BASE_HI, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 484 | (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 485 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 486 | /* |
| 487 | * Set the TZRAM size |
| 488 | * |
| 489 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 490 | * blocks) |
| 491 | * |
| 492 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 493 | val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 494 | total_128kb_blocks; |
| 495 | tegra_mc_write_32(MC_TZRAM_SIZE, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 496 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 497 | /* |
| 498 | * Lock the configuration settings by disabling TZ-only lock |
| 499 | * and locking the configuration against any future changes |
| 500 | * at all. |
| 501 | */ |
| 502 | val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 503 | val &= ~MC_GSC_ENABLE_TZ_LOCK_BIT; |
| 504 | val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 505 | tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 506 | |
| 507 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 508 | * MCE propagates the security configuration values across the |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 509 | * CCPLEX. |
| 510 | */ |
| 511 | mce_update_gsc_tzram(); |
| 512 | } |
| 513 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 514 | static void tegra_lock_videomem_nonoverlap(uint64_t phys_base, |
| 515 | uint64_t size_in_bytes) |
| 516 | { |
| 517 | uint32_t index; |
| 518 | uint64_t total_128kb_blocks = size_in_bytes >> 17; |
| 519 | uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
| 520 | uint64_t val; |
| 521 | |
| 522 | /* |
| 523 | * Reset the access configuration registers to restrict access to |
| 524 | * old Videomem aperture |
| 525 | */ |
| 526 | for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0; |
| 527 | index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 528 | index += 4U) { |
| 529 | tegra_mc_write_32(index, 0); |
| 530 | } |
| 531 | |
| 532 | /* |
| 533 | * Set the base. It must be 4k aligned, at least. |
| 534 | */ |
| 535 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
| 536 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base); |
| 537 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, |
| 538 | (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK); |
| 539 | |
| 540 | /* |
| 541 | * Set the aperture size |
| 542 | * |
| 543 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 544 | * blocks) |
| 545 | * |
| 546 | */ |
| 547 | val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
| 548 | total_128kb_blocks); |
| 549 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val); |
| 550 | |
| 551 | /* |
| 552 | * Lock the configuration settings by enabling TZ-only lock and |
| 553 | * locking the configuration against any future changes from NS |
| 554 | * world. |
| 555 | */ |
| 556 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG, |
| 557 | (uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT); |
| 558 | |
| 559 | /* |
| 560 | * MCE propagates the GSC configuration values across the |
| 561 | * CCPLEX. |
| 562 | */ |
| 563 | } |
| 564 | |
| 565 | static void tegra_unlock_videomem_nonoverlap(void) |
| 566 | { |
| 567 | /* Clear the base */ |
| 568 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0); |
| 569 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0); |
| 570 | |
| 571 | /* Clear the size */ |
| 572 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0); |
| 573 | } |
| 574 | |
| 575 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 576 | unsigned long long non_overlap_area_size) |
| 577 | { |
| 578 | /* |
| 579 | * Map the NS memory first, clean it and then unmap it. |
| 580 | */ |
| 581 | mmap_add_dynamic_region(non_overlap_area_start, /* PA */ |
| 582 | non_overlap_area_start, /* VA */ |
| 583 | non_overlap_area_size, /* size */ |
| 584 | MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ |
| 585 | |
| 586 | zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); |
| 587 | flush_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 588 | |
| 589 | mmap_remove_dynamic_region(non_overlap_area_start, |
| 590 | non_overlap_area_size); |
| 591 | } |
| 592 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 593 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 594 | * Program the Video Memory carveout region |
| 595 | * |
| 596 | * phys_base = physical base of aperture |
| 597 | * size_in_bytes = size of aperture in bytes |
| 598 | */ |
| 599 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 600 | { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 601 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20); |
| 602 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 603 | unsigned long long non_overlap_area_size; |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 604 | |
| 605 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 606 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 607 | * Memory region |
| 608 | */ |
| 609 | INFO("Configuring Video Memory Carveout\n"); |
| 610 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 611 | /* |
| 612 | * Configure Memory Controller directly for the first time. |
| 613 | */ |
| 614 | if (video_mem_base == 0U) |
| 615 | goto done; |
| 616 | |
| 617 | /* |
| 618 | * Lock the non overlapping memory being cleared so that other masters |
| 619 | * do not accidently write to it. The memory would be unlocked once |
| 620 | * the non overlapping region is cleared and the new memory |
| 621 | * settings take effect. |
| 622 | */ |
| 623 | tegra_lock_videomem_nonoverlap(video_mem_base, |
| 624 | video_mem_size_mb << 20); |
| 625 | |
| 626 | /* |
| 627 | * Clear the old regions now being exposed. The following cases |
| 628 | * can occur - |
| 629 | * |
| 630 | * 1. clear whole old region (no overlap with new region) |
| 631 | * 2. clear old sub-region below new base |
| 632 | * 3. clear old sub-region above new end |
| 633 | */ |
| 634 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 635 | |
| 636 | if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { |
| 637 | tegra_clear_videomem(video_mem_base, |
| 638 | (uint64_t)video_mem_size_mb << 20); |
| 639 | } else { |
| 640 | if (video_mem_base < phys_base) { |
| 641 | non_overlap_area_size = phys_base - video_mem_base; |
| 642 | tegra_clear_videomem(video_mem_base, non_overlap_area_size); |
| 643 | } |
| 644 | if (vmem_end_old > vmem_end_new) { |
| 645 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
| 646 | tegra_clear_videomem(vmem_end_new, non_overlap_area_size); |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | done: |
| 651 | /* program the Videomem aperture */ |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 652 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
| 653 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 654 | (uint32_t)(phys_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 655 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 656 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 657 | /* unlock the previous locked nonoverlapping aperture */ |
| 658 | tegra_unlock_videomem_nonoverlap(); |
| 659 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 660 | /* store new values */ |
| 661 | video_mem_base = phys_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 662 | video_mem_size_mb = size_in_bytes >> 20; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 663 | |
| 664 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 665 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 666 | * CCPLEX. |
| 667 | */ |
| 668 | mce_update_gsc_videomem(); |
| 669 | } |
Varun Wadekar | c92050b | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 670 | |
| 671 | /* |
| 672 | * This feature exists only for v1 of the Tegra Memory Controller. |
| 673 | */ |
| 674 | void tegra_memctrl_disable_ahb_redirection(void) |
| 675 | { |
| 676 | ; /* do nothing */ |
| 677 | } |