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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewb911cc72017-02-13 12:46:28 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#ifndef __PSCI_H__
8#define __PSCI_H__
9
Soby Mathew523d6332015-01-08 18:02:19 +000010#include <bakery_lock.h>
Soby Mathew89256b82016-09-13 14:19:08 +010011#include <bl_common.h>
Soby Mathew981487a2015-07-13 14:10:57 +010012#include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */
13#if ENABLE_PLAT_COMPAT
14#include <psci_compat.h>
15#endif
Soby Mathewb911cc72017-02-13 12:46:28 +000016#include <psci_lib.h> /* To maintain compatibility for SPDs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070017#include <utils_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010018
Achin Gupta4f6ad662013-10-25 09:08:21 +010019/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000020 * Number of power domains whose state this PSCI implementation can track
Soby Mathew523d6332015-01-08 18:02:19 +000021 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010022#ifdef PLAT_NUM_PWR_DOMAINS
23#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
Soby Mathew523d6332015-01-08 18:02:19 +000024#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -070025#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT)
Soby Mathew523d6332015-01-08 18:02:19 +000026#endif
27
Soby Mathew981487a2015-07-13 14:10:57 +010028#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
29 PLATFORM_CORE_COUNT)
30
31/* This is the power level corresponding to a CPU */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define PSCI_CPU_PWR_LVL (0)
Soby Mathew981487a2015-07-13 14:10:57 +010033
34/*
35 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND
36 * uses the old power_state parameter format which has 2 bits to specify the
37 * power level, this constant is defined to be 3.
38 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070039#define PSCI_MAX_PWR_LVL U(3)
Soby Mathew981487a2015-07-13 14:10:57 +010040
Soby Mathew523d6332015-01-08 18:02:19 +000041/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000042 * Defines for runtime services function ids
Achin Gupta4f6ad662013-10-25 09:08:21 +010043 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070044#define PSCI_VERSION U(0x84000000)
45#define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001)
46#define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001)
47#define PSCI_CPU_OFF U(0x84000002)
48#define PSCI_CPU_ON_AARCH32 U(0x84000003)
49#define PSCI_CPU_ON_AARCH64 U(0xc4000003)
50#define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004)
51#define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004)
52#define PSCI_MIG_AARCH32 U(0x84000005)
53#define PSCI_MIG_AARCH64 U(0xc4000005)
54#define PSCI_MIG_INFO_TYPE U(0x84000006)
55#define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007)
56#define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007)
57#define PSCI_SYSTEM_OFF U(0x84000008)
58#define PSCI_SYSTEM_RESET U(0x84000009)
59#define PSCI_FEATURES U(0x8400000A)
60#define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d)
61#define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d)
62#define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E)
63#define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E)
64#define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010)
65#define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010)
66#define PSCI_STAT_COUNT_AARCH32 U(0x84000011)
67#define PSCI_STAT_COUNT_AARCH64 U(0xc4000011)
Soby Mathew6cdddaf2015-01-07 11:10:22 +000068
69/* Macro to help build the psci capabilities bitfield */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070070#define define_psci_cap(x) (U(1) << (x & U(0x1f)))
Achin Gupta4f6ad662013-10-25 09:08:21 +010071
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000072/*
Juan Castillo4dc4a472014-08-12 11:17:06 +010073 * Number of PSCI calls (above) implemented
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000074 */
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010075#if ENABLE_PSCI_STAT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070076#define PSCI_NUM_CALLS U(22)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010077#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -070078#define PSCI_NUM_CALLS U(18)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010079#endif
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000080
Soby Mathewd0194872016-04-29 19:01:30 +010081/* The macros below are used to identify PSCI calls from the SMC function ID */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070082#define PSCI_FID_MASK U(0xffe0)
83#define PSCI_FID_VALUE U(0)
Soby Mathewd0194872016-04-29 19:01:30 +010084#define is_psci_fid(_fid) \
85 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE)
86
Achin Gupta4f6ad662013-10-25 09:08:21 +010087/*******************************************************************************
88 * PSCI Migrate and friends
89 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070090#define PSCI_TOS_UP_MIG_CAP U(0)
91#define PSCI_TOS_NOT_UP_MIG_CAP U(1)
92#define PSCI_TOS_NOT_PRESENT_MP U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010093
94/*******************************************************************************
95 * PSCI CPU_SUSPEND 'power_state' parameter specific defines
96 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070097#define PSTATE_ID_SHIFT U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010098
Soby Mathew981487a2015-07-13 14:10:57 +010099#if PSCI_EXTENDED_STATE_ID
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700100#define PSTATE_VALID_MASK U(0xB0000000)
101#define PSTATE_TYPE_SHIFT U(30)
102#define PSTATE_ID_MASK U(0xfffffff)
Soby Mathew981487a2015-07-13 14:10:57 +0100103#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700104#define PSTATE_VALID_MASK U(0xFCFE0000)
105#define PSTATE_TYPE_SHIFT U(16)
106#define PSTATE_PWR_LVL_SHIFT U(24)
107#define PSTATE_ID_MASK U(0xffff)
108#define PSTATE_PWR_LVL_MASK U(0x3)
Soby Mathew981487a2015-07-13 14:10:57 +0100109
110#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \
111 PSTATE_PWR_LVL_MASK)
112#define psci_make_powerstate(state_id, type, pwrlvl) \
113 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\
114 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\
115 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT)
116#endif /* __PSCI_EXTENDED_STATE_ID__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700118#define PSTATE_TYPE_STANDBY U(0x0)
119#define PSTATE_TYPE_POWERDOWN U(0x1)
120#define PSTATE_TYPE_MASK U(0x1)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000121
Soby Mathew96168382014-12-17 14:47:57 +0000122#define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \
Soby Mathew74e52a72014-10-02 16:56:51 +0100123 PSTATE_ID_MASK)
Soby Mathew96168382014-12-17 14:47:57 +0000124#define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \
Soby Mathew74e52a72014-10-02 16:56:51 +0100125 PSTATE_TYPE_MASK)
Soby Mathew981487a2015-07-13 14:10:57 +0100126#define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
128/*******************************************************************************
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000129 * PSCI CPU_FEATURES feature flag specific defines
130 ******************************************************************************/
131/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700132#define FF_PSTATE_SHIFT U(1)
133#define FF_PSTATE_ORIG U(0)
134#define FF_PSTATE_EXTENDED U(1)
Soby Mathew981487a2015-07-13 14:10:57 +0100135#if PSCI_EXTENDED_STATE_ID
136#define FF_PSTATE FF_PSTATE_EXTENDED
137#else
138#define FF_PSTATE FF_PSTATE_ORIG
139#endif
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000140
141/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700142#define FF_MODE_SUPPORT_SHIFT U(0)
143#define FF_SUPPORTS_OS_INIT_MODE U(1)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000144
145/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146 * PSCI version
147 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700148#define PSCI_MAJOR_VER (U(1) << 16)
149#define PSCI_MINOR_VER U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
151/*******************************************************************************
152 * PSCI error codes
153 ******************************************************************************/
154#define PSCI_E_SUCCESS 0
155#define PSCI_E_NOT_SUPPORTED -1
156#define PSCI_E_INVALID_PARAMS -2
157#define PSCI_E_DENIED -3
158#define PSCI_E_ALREADY_ON -4
159#define PSCI_E_ON_PENDING -5
160#define PSCI_E_INTERN_FAIL -6
161#define PSCI_E_NOT_PRESENT -7
162#define PSCI_E_DISABLED -8
Soby Mathewf1f97a12015-07-15 12:13:26 +0100163#define PSCI_E_INVALID_ADDRESS -9
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164
Soby Mathew011ca182015-07-29 17:05:03 +0100165#define PSCI_INVALID_MPIDR ~((u_register_t)0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166
Soby Mathew981487a2015-07-13 14:10:57 +0100167#ifndef __ASSEMBLY__
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168
Soby Mathew981487a2015-07-13 14:10:57 +0100169#include <stdint.h>
170#include <types.h>
171
172/*
173 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified
174 * CPU. The definitions of these states can be found in Section 5.7.1 in the
175 * PSCI specification (ARM DEN 0022C).
176 */
177typedef enum {
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700178 AFF_STATE_ON = U(0),
179 AFF_STATE_OFF = U(1),
180 AFF_STATE_ON_PENDING = U(2)
Soby Mathew981487a2015-07-13 14:10:57 +0100181} aff_info_state_t;
182
183/*
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100184 * These are the power states reported by PSCI_NODE_HW_STATE API for the
185 * specified CPU. The definitions of these states can be found in Section 5.15.3
186 * of PSCI specification (ARM DEN 0022C).
187 */
188typedef enum {
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700189 HW_ON = U(0),
190 HW_OFF = U(1),
191 HW_STANDBY = U(2)
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100192} node_hw_state_t;
193
194/*
Soby Mathew981487a2015-07-13 14:10:57 +0100195 * Macro to represent invalid affinity level within PSCI.
196 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700197#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100198
Soby Mathew981487a2015-07-13 14:10:57 +0100199/*
200 * Type for representing the local power state at a particular level.
201 */
202typedef uint8_t plat_local_state_t;
203
204/* The local state macro used to represent RUN state. */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700205#define PSCI_LOCAL_STATE_RUN U(0)
Achin Gupta75f73672013-12-05 16:33:10 +0000206
Soby Mathew981487a2015-07-13 14:10:57 +0100207/*
208 * Macro to test whether the plat_local_state is RUN state
209 */
210#define is_local_state_run(plat_local_state) \
211 ((plat_local_state) == PSCI_LOCAL_STATE_RUN)
Vikram Kanigirif100f412014-04-01 19:26:26 +0100212
Soby Mathew981487a2015-07-13 14:10:57 +0100213/*
214 * Macro to test whether the plat_local_state is RETENTION state
215 */
216#define is_local_state_retn(plat_local_state) \
217 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \
218 ((plat_local_state) <= PLAT_MAX_RET_STATE))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100219
Soby Mathew981487a2015-07-13 14:10:57 +0100220/*
221 * Macro to test whether the plat_local_state is OFF state
222 */
223#define is_local_state_off(plat_local_state) \
224 (((plat_local_state) > PLAT_MAX_RET_STATE) && \
225 ((plat_local_state) <= PLAT_MAX_OFF_STATE))
Dan Handley2bd4ef22014-04-09 13:14:54 +0100226
Soby Mathew981487a2015-07-13 14:10:57 +0100227/*****************************************************************************
228 * This data structure defines the representation of the power state parameter
229 * for its exchange between the generic PSCI code and the platform port. For
230 * example, it is used by the platform port to specify the requested power
231 * states during a power management operation. It is used by the generic code to
232 * inform the platform about the target power states that each level should
233 * enter.
234 ****************************************************************************/
235typedef struct psci_power_state {
236 /*
237 * The pwr_domain_state[] stores the local power state at each level
238 * for the CPU.
239 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700240 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)];
Soby Mathew981487a2015-07-13 14:10:57 +0100241} psci_power_state_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100242
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100243/*******************************************************************************
244 * Structure used to store per-cpu information relevant to the PSCI service.
245 * It is populated in the per-cpu data array. In return we get a guarantee that
246 * this information will not reside on a cache line shared with another cpu.
247 ******************************************************************************/
248typedef struct psci_cpu_data {
Soby Mathew981487a2015-07-13 14:10:57 +0100249 /* State as seen by PSCI Affinity Info API */
250 aff_info_state_t aff_info_state;
Soby Mathew011ca182015-07-29 17:05:03 +0100251
Soby Mathew981487a2015-07-13 14:10:57 +0100252 /*
253 * Highest power level which takes part in a power management
254 * operation.
255 */
Soby Mathew011ca182015-07-29 17:05:03 +0100256 unsigned char target_pwrlvl;
257
Soby Mathew981487a2015-07-13 14:10:57 +0100258 /* The local power state of this CPU */
259 plat_local_state_t local_state;
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100260} psci_cpu_data_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100261
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262/*******************************************************************************
263 * Structure populated by platform specific code to export routines which
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000264 * perform common low level power management functions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100265 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100266typedef struct plat_psci_ops {
267 void (*cpu_standby)(plat_local_state_t cpu_state);
268 int (*pwr_domain_on)(u_register_t mpidr);
269 void (*pwr_domain_off)(const psci_power_state_t *target_state);
Varun Wadekarae87f4b2017-07-10 16:02:05 -0700270 void (*pwr_domain_suspend_pwrdown_early)(
271 const psci_power_state_t *target_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100272 void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
273 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
274 void (*pwr_domain_suspend_finish)(
275 const psci_power_state_t *target_state);
Soby Mathew6a816412016-04-27 14:46:28 +0100276 void (*pwr_domain_pwr_down_wfi)(
277 const psci_power_state_t *target_state) __dead2;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100278 void (*system_off)(void) __dead2;
279 void (*system_reset)(void) __dead2;
Soby Mathew981487a2015-07-13 14:10:57 +0100280 int (*validate_power_state)(unsigned int power_state,
281 psci_power_state_t *req_state);
Soby Mathew011ca182015-07-29 17:05:03 +0100282 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
Soby Mathew981487a2015-07-13 14:10:57 +0100283 void (*get_sys_suspend_power_state)(
284 psci_power_state_t *req_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100285 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
286 int pwrlvl);
287 int (*translate_power_state_by_mpidr)(u_register_t mpidr,
288 unsigned int power_state,
289 psci_power_state_t *output_state);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100290 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
Soby Mathew981487a2015-07-13 14:10:57 +0100291} plat_psci_ops_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292
293/*******************************************************************************
294 * Function & Data prototypes
295 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100296unsigned int psci_version(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100297int psci_cpu_on(u_register_t target_cpu,
298 uintptr_t entrypoint,
299 u_register_t context_id);
300int psci_cpu_suspend(unsigned int power_state,
301 uintptr_t entrypoint,
302 u_register_t context_id);
303int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id);
304int psci_cpu_off(void);
305int psci_affinity_info(u_register_t target_affinity,
306 unsigned int lowest_affinity_level);
307int psci_migrate(u_register_t target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100308int psci_migrate_info_type(void);
309long psci_migrate_info_up_cpu(void);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100310int psci_node_hw_state(u_register_t target_cpu,
311 unsigned int power_level);
Soby Mathew011ca182015-07-29 17:05:03 +0100312int psci_features(unsigned int psci_fid);
Dan Handleya17fefa2014-05-14 12:38:32 +0100313void __dead2 psci_power_down_wfi(void);
Soby Mathewd0194872016-04-29 19:01:30 +0100314void psci_arch_setup(void);
315
316/*
317 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in
318 * AArch64.
319 */
320void psci_entrypoint(void) __deprecated;
321
Achin Gupta4f6ad662013-10-25 09:08:21 +0100322#endif /*__ASSEMBLY__*/
323
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324#endif /* __PSCI_H__ */