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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
34#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010035#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
Dan Handleye2712bc2014-04-10 15:37:22 +010037typedef int (*afflvl_off_handler_t)(unsigned long, aff_map_node_t *);
Achin Gupta4f6ad662013-10-25 09:08:21 +010038
39/*******************************************************************************
40 * The next three functions implement a handler for each supported affinity
41 * level which is called when that affinity level is turned off.
42 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010043static int psci_afflvl0_off(unsigned long mpidr, aff_map_node_t *cpu_node)
Achin Gupta4f6ad662013-10-25 09:08:21 +010044{
45 unsigned int index, plat_state;
46 int rc = PSCI_E_SUCCESS;
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000047 unsigned long sctlr;
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
49 assert(cpu_node->level == MPIDR_AFFLVL0);
50
Achin Gupta75f73672013-12-05 16:33:10 +000051 /* State management: mark this cpu as turned off */
52 psci_set_state(cpu_node, PSCI_STATE_OFF);
53
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 /*
Achin Gupta607084e2014-02-09 18:24:19 +000055 * Generic management: Get the index for clearing any lingering re-entry
56 * information and allow the secure world to switch itself off
57 */
58
59 /*
60 * Call the cpu off handler registered by the Secure Payload Dispatcher
61 * to let it do any bookeeping. Assume that the SPD always reports an
62 * E_DENIED error if SP refuse to power down
Achin Gupta4f6ad662013-10-25 09:08:21 +010063 */
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000064 if (psci_spd_pm && psci_spd_pm->svc_off) {
65 rc = psci_spd_pm->svc_off(0);
Achin Gupta607084e2014-02-09 18:24:19 +000066 if (rc)
67 return rc;
68 }
69
Achin Gupta4f6ad662013-10-25 09:08:21 +010070 index = cpu_node->data;
71 memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index]));
72
73 /*
74 * Arch. management. Perform the necessary steps to flush all
75 * cpu caches.
76 *
77 * TODO: This power down sequence varies across cpus so it needs to be
78 * abstracted out on the basis of the MIDR like in cpu_reset_handler().
79 * Do the bare minimal for the time being. Fix this before porting to
80 * Cortex models.
81 */
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000082 sctlr = read_sctlr_el3();
Achin Gupta4f6ad662013-10-25 09:08:21 +010083 sctlr &= ~SCTLR_C_BIT;
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000084 write_sctlr_el3(sctlr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010085
86 /*
87 * CAUTION: This flush to the level of unification makes an assumption
88 * about the cache hierarchy at affinity level 0 (cpu) in the platform.
89 * Ideally the platform should tell psci which levels to flush to exit
90 * coherency.
91 */
92 dcsw_op_louis(DCCISW);
93
94 /*
95 * Plat. management: Perform platform specific actions to turn this
96 * cpu off e.g. exit cpu coherency, program the power controller etc.
97 */
98 if (psci_plat_pm_ops->affinst_off) {
99
100 /* Get the current physical state of this cpu */
Achin Gupta75f73672013-12-05 16:33:10 +0000101 plat_state = psci_get_phys_state(cpu_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102 rc = psci_plat_pm_ops->affinst_off(mpidr,
103 cpu_node->level,
104 plat_state);
105 }
106
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 return rc;
108}
109
Dan Handleye2712bc2014-04-10 15:37:22 +0100110static int psci_afflvl1_off(unsigned long mpidr, aff_map_node_t *cluster_node)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111{
112 int rc = PSCI_E_SUCCESS;
113 unsigned int plat_state;
114
115 /* Sanity check the cluster level */
116 assert(cluster_node->level == MPIDR_AFFLVL1);
117
Achin Gupta75f73672013-12-05 16:33:10 +0000118 /* State management: Decrement the cluster reference count */
119 psci_set_state(cluster_node, PSCI_STATE_OFF);
120
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 /*
122 * Keep the physical state of this cluster handy to decide
123 * what action needs to be taken
124 */
Achin Gupta75f73672013-12-05 16:33:10 +0000125 plat_state = psci_get_phys_state(cluster_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126
127 /*
128 * Arch. Management. Flush all levels of caches to PoC if
129 * the cluster is to be shutdown
130 */
131 if (plat_state == PSCI_STATE_OFF)
132 dcsw_op_all(DCCISW);
133
134 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000135 * Plat. Management. Allow the platform to do its cluster
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 * specific bookeeping e.g. turn off interconnect coherency,
137 * program the power controller etc.
138 */
139 if (psci_plat_pm_ops->affinst_off)
140 rc = psci_plat_pm_ops->affinst_off(mpidr,
141 cluster_node->level,
142 plat_state);
143
144 return rc;
145}
146
Dan Handleye2712bc2014-04-10 15:37:22 +0100147static int psci_afflvl2_off(unsigned long mpidr, aff_map_node_t *system_node)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148{
149 int rc = PSCI_E_SUCCESS;
150 unsigned int plat_state;
151
152 /* Cannot go beyond this level */
153 assert(system_node->level == MPIDR_AFFLVL2);
154
Achin Gupta75f73672013-12-05 16:33:10 +0000155 /* State management: Decrement the system reference count */
156 psci_set_state(system_node, PSCI_STATE_OFF);
157
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158 /*
159 * Keep the physical state of the system handy to decide what
160 * action needs to be taken
161 */
Achin Gupta75f73672013-12-05 16:33:10 +0000162 plat_state = psci_get_phys_state(system_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163
164 /* No arch. and generic bookeeping to do here currently */
165
166 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000167 * Plat. Management : Allow the platform to do its bookeeping
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168 * at this affinity level
169 */
170 if (psci_plat_pm_ops->affinst_off)
171 rc = psci_plat_pm_ops->affinst_off(mpidr,
172 system_node->level,
173 plat_state);
174 return rc;
175}
176
Dan Handleye2712bc2014-04-10 15:37:22 +0100177static const afflvl_off_handler_t psci_afflvl_off_handlers[] = {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178 psci_afflvl0_off,
179 psci_afflvl1_off,
180 psci_afflvl2_off,
181};
182
183/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000184 * This function takes an array of pointers to affinity instance nodes in the
185 * topology tree and calls the off handler for the corresponding affinity
186 * levels
187 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100188static int psci_call_off_handlers(mpidr_aff_map_nodes_t mpidr_nodes,
Achin Gupta0959db52013-12-02 17:33:04 +0000189 int start_afflvl,
190 int end_afflvl,
191 unsigned long mpidr)
192{
193 int rc = PSCI_E_INVALID_PARAMS, level;
Dan Handleye2712bc2014-04-10 15:37:22 +0100194 aff_map_node_t *node;
Achin Gupta0959db52013-12-02 17:33:04 +0000195
196 for (level = start_afflvl; level <= end_afflvl; level++) {
197 node = mpidr_nodes[level];
198 if (node == NULL)
199 continue;
200
201 /*
202 * TODO: In case of an error should there be a way
203 * of restoring what we might have torn down at
204 * lower affinity levels.
205 */
206 rc = psci_afflvl_off_handlers[level](mpidr, node);
207 if (rc != PSCI_E_SUCCESS)
208 break;
209 }
210
211 return rc;
212}
213
214/*******************************************************************************
215 * Top level handler which is called when a cpu wants to power itself down.
216 * It's assumed that along with turning the cpu off, higher affinity levels will
217 * be turned off as far as possible. It traverses through all the affinity
218 * levels performing generic, architectural, platform setup and state management
219 * e.g. for a cluster that's to be powered off, it will call the platform
220 * specific code which will disable coherency at the interconnect level if the
221 * cpu is the last in the cluster. For a cpu it could mean programming the power
222 * the power controller etc.
223 *
224 * The state of all the relevant affinity levels is changed prior to calling the
225 * affinity level specific handlers as their actions would depend upon the state
226 * the affinity level is about to enter.
227 *
228 * The affinity level specific handlers are called in ascending order i.e. from
229 * the lowest to the highest affinity level implemented by the platform because
230 * to turn off affinity level X it is neccesary to turn off affinity level X - 1
231 * first.
232 *
233 * CAUTION: This function is called with coherent stacks so that coherency can
234 * be turned off and caches can be flushed safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235 ******************************************************************************/
236int psci_afflvl_off(unsigned long mpidr,
Achin Gupta0959db52013-12-02 17:33:04 +0000237 int start_afflvl,
238 int end_afflvl)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239{
Achin Gupta0959db52013-12-02 17:33:04 +0000240 int rc = PSCI_E_SUCCESS;
Dan Handleye2712bc2014-04-10 15:37:22 +0100241 mpidr_aff_map_nodes_t mpidr_nodes;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242
243 mpidr &= MPIDR_AFFINITY_MASK;;
244
245 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000246 * Collect the pointers to the nodes in the topology tree for
247 * each affinity instance in the mpidr. If this function does
248 * not return successfully then either the mpidr or the affinity
249 * levels are incorrect. In either case, we cannot return back
250 * to the caller as it would not know what to do.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251 */
Achin Gupta0959db52013-12-02 17:33:04 +0000252 rc = psci_get_aff_map_nodes(mpidr,
253 start_afflvl,
254 end_afflvl,
255 mpidr_nodes);
256 assert (rc == PSCI_E_SUCCESS);
257
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000259 * This function acquires the lock corresponding to each affinity
260 * level so that by the time all locks are taken, the system topology
261 * is snapshot and state management can be done safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262 */
Achin Gupta0959db52013-12-02 17:33:04 +0000263 psci_acquire_afflvl_locks(mpidr,
264 start_afflvl,
265 end_afflvl,
266 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100267
Achin Gupta0959db52013-12-02 17:33:04 +0000268 /* Perform generic, architecture and platform specific handling */
269 rc = psci_call_off_handlers(mpidr_nodes,
270 start_afflvl,
271 end_afflvl,
272 mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273
274 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000275 * Release the locks corresponding to each affinity level in the
276 * reverse order to which they were acquired.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277 */
Achin Gupta0959db52013-12-02 17:33:04 +0000278 psci_release_afflvl_locks(mpidr,
279 start_afflvl,
280 end_afflvl,
281 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100282
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283 return rc;
284}