Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | 8f268c8 | 2020-02-26 13:39:44 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP1_DEF_H |
| 8 | #define STM32MP1_DEF_H |
| 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/tbbr/tbbr_img_def.h> |
Yann Gautier | b5d2ed4 | 2019-02-14 11:13:50 +0100 | [diff] [blame] | 11 | #include <drivers/st/stm32mp1_rcc.h> |
| 12 | #include <dt-bindings/clock/stm32mp1-clks.h> |
| 13 | #include <dt-bindings/reset/stm32mp1-resets.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <lib/utils_def.h> |
| 15 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 16 | |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 17 | #ifndef __ASSEMBLER__ |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 18 | #include <drivers/st/bsec.h> |
Yann Gautier | b5d2ed4 | 2019-02-14 11:13:50 +0100 | [diff] [blame] | 19 | #include <drivers/st/stm32mp1_clk.h> |
| 20 | |
Yann Gautier | 57e282b | 2019-01-07 11:17:24 +0100 | [diff] [blame] | 21 | #include <boot_api.h> |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 22 | #include <stm32mp_auth.h> |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 23 | #include <stm32mp_common.h> |
| 24 | #include <stm32mp_dt.h> |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 25 | #include <stm32mp_shres_helpers.h> |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 26 | #include <stm32mp1_dbgmcu.h> |
Yann Gautier | 57e282b | 2019-01-07 11:17:24 +0100 | [diff] [blame] | 27 | #include <stm32mp1_private.h> |
Etienne Carriere | 316d634 | 2019-12-02 10:08:48 +0100 | [diff] [blame] | 28 | #include <stm32mp1_shared_resources.h> |
Yann Gautier | 57e282b | 2019-01-07 11:17:24 +0100 | [diff] [blame] | 29 | #endif |
| 30 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 31 | /******************************************************************************* |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 32 | * CHIP ID |
| 33 | ******************************************************************************/ |
| 34 | #define STM32MP157C_PART_NB U(0x05000000) |
| 35 | #define STM32MP157A_PART_NB U(0x05000001) |
| 36 | #define STM32MP153C_PART_NB U(0x05000024) |
| 37 | #define STM32MP153A_PART_NB U(0x05000025) |
| 38 | #define STM32MP151C_PART_NB U(0x0500002E) |
| 39 | #define STM32MP151A_PART_NB U(0x0500002F) |
| 40 | |
| 41 | #define STM32MP1_REV_B U(0x2000) |
Lionel Debieve | 2d64b53 | 2019-06-25 10:40:37 +0200 | [diff] [blame] | 42 | #define STM32MP1_REV_Z U(0x2001) |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 43 | |
| 44 | /******************************************************************************* |
| 45 | * PACKAGE ID |
| 46 | ******************************************************************************/ |
| 47 | #define PKG_AA_LFBGA448 U(4) |
| 48 | #define PKG_AB_LFBGA354 U(3) |
| 49 | #define PKG_AC_TFBGA361 U(2) |
| 50 | #define PKG_AD_TFBGA257 U(1) |
| 51 | |
| 52 | /******************************************************************************* |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 53 | * STM32MP1 memory map related constants |
| 54 | ******************************************************************************/ |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 55 | #define STM32MP_ROM_BASE U(0x00000000) |
| 56 | #define STM32MP_ROM_SIZE U(0x00020000) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 57 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 58 | #define STM32MP_SYSRAM_BASE U(0x2FFC0000) |
| 59 | #define STM32MP_SYSRAM_SIZE U(0x00040000) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 60 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 61 | #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE |
| 62 | #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ |
| 63 | STM32MP_SYSRAM_SIZE - \ |
| 64 | STM32MP_NS_SYSRAM_SIZE) |
| 65 | |
Etienne Carriere | 34f0e93 | 2020-07-16 17:36:18 +0200 | [diff] [blame] | 66 | #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE |
| 67 | #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE |
| 68 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 69 | #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE |
| 70 | #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ |
| 71 | STM32MP_NS_SYSRAM_SIZE) |
| 72 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 73 | /* DDR configuration */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 74 | #define STM32MP_DDR_BASE U(0xC0000000) |
| 75 | #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 76 | #ifdef AARCH32_SP_OPTEE |
| 77 | #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ |
| 78 | #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ |
Yann Gautier | 8f268c8 | 2020-02-26 13:39:44 +0100 | [diff] [blame] | 79 | #else |
| 80 | #define STM32MP_DDR_S_SIZE U(0) |
| 81 | #define STM32MP_DDR_SHMEM_SIZE U(0) |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 82 | #endif |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 83 | |
| 84 | /* DDR power initializations */ |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 85 | #ifndef __ASSEMBLER__ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 86 | enum ddr_type { |
| 87 | STM32MP_DDR3, |
| 88 | STM32MP_LPDDR2, |
Yann Gautier | 917a00c | 2019-04-16 16:20:58 +0200 | [diff] [blame] | 89 | STM32MP_LPDDR3 |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 90 | }; |
| 91 | #endif |
| 92 | |
| 93 | /* Section used inside TF binaries */ |
Nicolas Le Bayon | 0708441 | 2019-09-27 11:05:31 +0200 | [diff] [blame] | 94 | #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 95 | /* 256 Octets reserved for header */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 96 | #define STM32MP_HEADER_SIZE U(0x00000100) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 97 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 98 | #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 99 | STM32MP_PARAM_LOAD_SIZE + \ |
| 100 | STM32MP_HEADER_SIZE) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 101 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 102 | #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 103 | (STM32MP_PARAM_LOAD_SIZE + \ |
| 104 | STM32MP_HEADER_SIZE)) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 105 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 106 | #ifdef AARCH32_SP_OPTEE |
| 107 | #define STM32MP_BL32_SIZE U(0) |
| 108 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 109 | #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 110 | |
| 111 | #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ |
| 112 | STM32MP_OPTEE_BASE) |
| 113 | #else |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 114 | #if STACK_PROTECTOR_ENABLED |
Nicolas Le Bayon | 0708441 | 2019-09-27 11:05:31 +0200 | [diff] [blame] | 115 | #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 116 | #else |
Nicolas Le Bayon | 0708441 | 2019-09-27 11:05:31 +0200 | [diff] [blame] | 117 | #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 118 | #endif |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 119 | #endif |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 120 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 121 | #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ |
| 122 | STM32MP_SEC_SYSRAM_SIZE - \ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 123 | STM32MP_BL32_SIZE) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 124 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 125 | #ifdef AARCH32_SP_OPTEE |
| 126 | #if STACK_PROTECTOR_ENABLED |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 127 | #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 128 | #else |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 129 | #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 130 | #endif |
| 131 | #else |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 132 | #if STACK_PROTECTOR_ENABLED |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 133 | #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 134 | #else |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 135 | #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 136 | #endif |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 137 | #endif |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 138 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 139 | #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ |
| 140 | STM32MP_BL2_SIZE) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 141 | |
Nicolas Le Bayon | 0708441 | 2019-09-27 11:05:31 +0200 | [diff] [blame] | 142 | /* BL2 and BL32/sp_min require 4 tables */ |
| 143 | #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * MAX_MMAP_REGIONS is usually: |
| 147 | * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup |
| 148 | */ |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 149 | #if defined(IMAGE_BL2) |
| 150 | #define MAX_MMAP_REGIONS 11 |
| 151 | #endif |
| 152 | #if defined(IMAGE_BL32) |
| 153 | #define MAX_MMAP_REGIONS 6 |
| 154 | #endif |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 155 | |
| 156 | /* DTB initialization value */ |
Nicolas Le Bayon | 0708441 | 2019-09-27 11:05:31 +0200 | [diff] [blame] | 157 | #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 158 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 159 | #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ |
| 160 | STM32MP_DTB_SIZE) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 161 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 162 | #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 163 | |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 164 | /* Define maximum page size for NAND devices */ |
| 165 | #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) |
| 166 | |
| 167 | /******************************************************************************* |
| 168 | * STM32MP1 RAW partition offset for MTD devices |
| 169 | ******************************************************************************/ |
Lionel Debieve | cb0dbc4 | 2019-09-25 09:11:31 +0200 | [diff] [blame] | 170 | #define STM32MP_NOR_BL33_OFFSET U(0x00080000) |
| 171 | #ifdef AARCH32_SP_OPTEE |
| 172 | #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) |
| 173 | #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) |
| 174 | #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) |
| 175 | #endif |
| 176 | |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 177 | #define STM32MP_NAND_BL33_OFFSET U(0x00200000) |
| 178 | #ifdef AARCH32_SP_OPTEE |
| 179 | #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) |
| 180 | #define STM32MP_NAND_TEED_OFFSET U(0x00680000) |
| 181 | #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) |
| 182 | #endif |
| 183 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 184 | /******************************************************************************* |
| 185 | * STM32MP1 device/io map related constants (used for MMU) |
| 186 | ******************************************************************************/ |
| 187 | #define STM32MP1_DEVICE1_BASE U(0x40000000) |
| 188 | #define STM32MP1_DEVICE1_SIZE U(0x40000000) |
| 189 | |
| 190 | #define STM32MP1_DEVICE2_BASE U(0x80000000) |
| 191 | #define STM32MP1_DEVICE2_SIZE U(0x40000000) |
| 192 | |
| 193 | /******************************************************************************* |
| 194 | * STM32MP1 RCC |
| 195 | ******************************************************************************/ |
| 196 | #define RCC_BASE U(0x50000000) |
| 197 | |
| 198 | /******************************************************************************* |
| 199 | * STM32MP1 PWR |
| 200 | ******************************************************************************/ |
| 201 | #define PWR_BASE U(0x50001000) |
| 202 | |
| 203 | /******************************************************************************* |
Yann Gautier | 038bff2 | 2019-01-17 19:17:47 +0100 | [diff] [blame] | 204 | * STM32MP1 GPIO |
| 205 | ******************************************************************************/ |
| 206 | #define GPIOA_BASE U(0x50002000) |
| 207 | #define GPIOB_BASE U(0x50003000) |
| 208 | #define GPIOC_BASE U(0x50004000) |
| 209 | #define GPIOD_BASE U(0x50005000) |
| 210 | #define GPIOE_BASE U(0x50006000) |
| 211 | #define GPIOF_BASE U(0x50007000) |
| 212 | #define GPIOG_BASE U(0x50008000) |
| 213 | #define GPIOH_BASE U(0x50009000) |
| 214 | #define GPIOI_BASE U(0x5000A000) |
| 215 | #define GPIOJ_BASE U(0x5000B000) |
| 216 | #define GPIOK_BASE U(0x5000C000) |
| 217 | #define GPIOZ_BASE U(0x54004000) |
| 218 | #define GPIO_BANK_OFFSET U(0x1000) |
| 219 | |
| 220 | /* Bank IDs used in GPIO driver API */ |
| 221 | #define GPIO_BANK_A U(0) |
| 222 | #define GPIO_BANK_B U(1) |
| 223 | #define GPIO_BANK_C U(2) |
| 224 | #define GPIO_BANK_D U(3) |
| 225 | #define GPIO_BANK_E U(4) |
| 226 | #define GPIO_BANK_F U(5) |
| 227 | #define GPIO_BANK_G U(6) |
| 228 | #define GPIO_BANK_H U(7) |
| 229 | #define GPIO_BANK_I U(8) |
| 230 | #define GPIO_BANK_J U(9) |
| 231 | #define GPIO_BANK_K U(10) |
| 232 | #define GPIO_BANK_Z U(25) |
| 233 | |
| 234 | #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 |
| 235 | |
| 236 | /******************************************************************************* |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 237 | * STM32MP1 UART |
| 238 | ******************************************************************************/ |
| 239 | #define USART1_BASE U(0x5C000000) |
| 240 | #define USART2_BASE U(0x4000E000) |
| 241 | #define USART3_BASE U(0x4000F000) |
| 242 | #define UART4_BASE U(0x40010000) |
| 243 | #define UART5_BASE U(0x40011000) |
| 244 | #define USART6_BASE U(0x44003000) |
| 245 | #define UART7_BASE U(0x40018000) |
| 246 | #define UART8_BASE U(0x40019000) |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 247 | #define STM32MP_UART_BAUDRATE U(115200) |
Yann Gautier | 038bff2 | 2019-01-17 19:17:47 +0100 | [diff] [blame] | 248 | |
| 249 | /* For UART crash console */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 250 | #define STM32MP_DEBUG_USART_BASE UART4_BASE |
Yann Gautier | 038bff2 | 2019-01-17 19:17:47 +0100 | [diff] [blame] | 251 | /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 252 | #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 |
Yann Gautier | 038bff2 | 2019-01-17 19:17:47 +0100 | [diff] [blame] | 253 | #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE |
| 254 | #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR |
| 255 | #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN |
| 256 | #define DEBUG_UART_TX_GPIO_PORT 11 |
| 257 | #define DEBUG_UART_TX_GPIO_ALTERNATE 6 |
| 258 | #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR |
| 259 | #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI |
| 260 | #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR |
| 261 | #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 262 | |
| 263 | /******************************************************************************* |
Etienne Carriere | e96162e | 2020-04-10 11:32:54 +0200 | [diff] [blame] | 264 | * STM32MP1 ETZPC |
| 265 | ******************************************************************************/ |
| 266 | #define STM32MP1_ETZPC_BASE U(0x5C007000) |
| 267 | |
| 268 | /* ETZPC TZMA IDs */ |
| 269 | #define STM32MP1_ETZPC_TZMA_ROM U(0) |
| 270 | #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) |
| 271 | |
| 272 | #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) |
| 273 | |
| 274 | /* ETZPC DECPROT IDs */ |
| 275 | #define STM32MP1_ETZPC_STGENC_ID 0 |
| 276 | #define STM32MP1_ETZPC_BKPSRAM_ID 1 |
| 277 | #define STM32MP1_ETZPC_IWDG1_ID 2 |
| 278 | #define STM32MP1_ETZPC_USART1_ID 3 |
| 279 | #define STM32MP1_ETZPC_SPI6_ID 4 |
| 280 | #define STM32MP1_ETZPC_I2C4_ID 5 |
| 281 | #define STM32MP1_ETZPC_RNG1_ID 7 |
| 282 | #define STM32MP1_ETZPC_HASH1_ID 8 |
| 283 | #define STM32MP1_ETZPC_CRYP1_ID 9 |
| 284 | #define STM32MP1_ETZPC_DDRCTRL_ID 10 |
| 285 | #define STM32MP1_ETZPC_DDRPHYC_ID 11 |
| 286 | #define STM32MP1_ETZPC_I2C6_ID 12 |
| 287 | #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 |
| 288 | |
| 289 | #define STM32MP1_ETZPC_TIM2_ID 16 |
| 290 | #define STM32MP1_ETZPC_TIM3_ID 17 |
| 291 | #define STM32MP1_ETZPC_TIM4_ID 18 |
| 292 | #define STM32MP1_ETZPC_TIM5_ID 19 |
| 293 | #define STM32MP1_ETZPC_TIM6_ID 20 |
| 294 | #define STM32MP1_ETZPC_TIM7_ID 21 |
| 295 | #define STM32MP1_ETZPC_TIM12_ID 22 |
| 296 | #define STM32MP1_ETZPC_TIM13_ID 23 |
| 297 | #define STM32MP1_ETZPC_TIM14_ID 24 |
| 298 | #define STM32MP1_ETZPC_LPTIM1_ID 25 |
| 299 | #define STM32MP1_ETZPC_WWDG1_ID 26 |
| 300 | #define STM32MP1_ETZPC_SPI2_ID 27 |
| 301 | #define STM32MP1_ETZPC_SPI3_ID 28 |
| 302 | #define STM32MP1_ETZPC_SPDIFRX_ID 29 |
| 303 | #define STM32MP1_ETZPC_USART2_ID 30 |
| 304 | #define STM32MP1_ETZPC_USART3_ID 31 |
| 305 | #define STM32MP1_ETZPC_UART4_ID 32 |
| 306 | #define STM32MP1_ETZPC_UART5_ID 33 |
| 307 | #define STM32MP1_ETZPC_I2C1_ID 34 |
| 308 | #define STM32MP1_ETZPC_I2C2_ID 35 |
| 309 | #define STM32MP1_ETZPC_I2C3_ID 36 |
| 310 | #define STM32MP1_ETZPC_I2C5_ID 37 |
| 311 | #define STM32MP1_ETZPC_CEC_ID 38 |
| 312 | #define STM32MP1_ETZPC_DAC_ID 39 |
| 313 | #define STM32MP1_ETZPC_UART7_ID 40 |
| 314 | #define STM32MP1_ETZPC_UART8_ID 41 |
| 315 | #define STM32MP1_ETZPC_MDIOS_ID 44 |
| 316 | #define STM32MP1_ETZPC_TIM1_ID 48 |
| 317 | #define STM32MP1_ETZPC_TIM8_ID 49 |
| 318 | #define STM32MP1_ETZPC_USART6_ID 51 |
| 319 | #define STM32MP1_ETZPC_SPI1_ID 52 |
| 320 | #define STM32MP1_ETZPC_SPI4_ID 53 |
| 321 | #define STM32MP1_ETZPC_TIM15_ID 54 |
| 322 | #define STM32MP1_ETZPC_TIM16_ID 55 |
| 323 | #define STM32MP1_ETZPC_TIM17_ID 56 |
| 324 | #define STM32MP1_ETZPC_SPI5_ID 57 |
| 325 | #define STM32MP1_ETZPC_SAI1_ID 58 |
| 326 | #define STM32MP1_ETZPC_SAI2_ID 59 |
| 327 | #define STM32MP1_ETZPC_SAI3_ID 60 |
| 328 | #define STM32MP1_ETZPC_DFSDM_ID 61 |
| 329 | #define STM32MP1_ETZPC_TT_FDCAN_ID 62 |
| 330 | #define STM32MP1_ETZPC_LPTIM2_ID 64 |
| 331 | #define STM32MP1_ETZPC_LPTIM3_ID 65 |
| 332 | #define STM32MP1_ETZPC_LPTIM4_ID 66 |
| 333 | #define STM32MP1_ETZPC_LPTIM5_ID 67 |
| 334 | #define STM32MP1_ETZPC_SAI4_ID 68 |
| 335 | #define STM32MP1_ETZPC_VREFBUF_ID 69 |
| 336 | #define STM32MP1_ETZPC_DCMI_ID 70 |
| 337 | #define STM32MP1_ETZPC_CRC2_ID 71 |
| 338 | #define STM32MP1_ETZPC_ADC_ID 72 |
| 339 | #define STM32MP1_ETZPC_HASH2_ID 73 |
| 340 | #define STM32MP1_ETZPC_RNG2_ID 74 |
| 341 | #define STM32MP1_ETZPC_CRYP2_ID 75 |
| 342 | #define STM32MP1_ETZPC_SRAM1_ID 80 |
| 343 | #define STM32MP1_ETZPC_SRAM2_ID 81 |
| 344 | #define STM32MP1_ETZPC_SRAM3_ID 82 |
| 345 | #define STM32MP1_ETZPC_SRAM4_ID 83 |
| 346 | #define STM32MP1_ETZPC_RETRAM_ID 84 |
| 347 | #define STM32MP1_ETZPC_OTG_ID 85 |
| 348 | #define STM32MP1_ETZPC_SDMMC3_ID 86 |
| 349 | #define STM32MP1_ETZPC_DLYBSD3_ID 87 |
| 350 | #define STM32MP1_ETZPC_DMA1_ID 88 |
| 351 | #define STM32MP1_ETZPC_DMA2_ID 89 |
| 352 | #define STM32MP1_ETZPC_DMAMUX_ID 90 |
| 353 | #define STM32MP1_ETZPC_FMC_ID 91 |
| 354 | #define STM32MP1_ETZPC_QSPI_ID 92 |
| 355 | #define STM32MP1_ETZPC_DLYBQ_ID 93 |
| 356 | #define STM32MP1_ETZPC_ETH_ID 94 |
| 357 | #define STM32MP1_ETZPC_RSV_ID 95 |
| 358 | |
| 359 | #define STM32MP_ETZPC_MAX_ID 96 |
| 360 | |
| 361 | /******************************************************************************* |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 362 | * STM32MP1 TZC (TZ400) |
| 363 | ******************************************************************************/ |
| 364 | #define STM32MP1_TZC_BASE U(0x5C006000) |
| 365 | |
| 366 | #define STM32MP1_TZC_A7_ID U(0) |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 367 | #define STM32MP1_TZC_M4_ID U(1) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 368 | #define STM32MP1_TZC_LCD_ID U(3) |
| 369 | #define STM32MP1_TZC_GPU_ID U(4) |
| 370 | #define STM32MP1_TZC_MDMA_ID U(5) |
| 371 | #define STM32MP1_TZC_DMA_ID U(6) |
| 372 | #define STM32MP1_TZC_USB_HOST_ID U(7) |
| 373 | #define STM32MP1_TZC_USB_OTG_ID U(8) |
| 374 | #define STM32MP1_TZC_SDMMC_ID U(9) |
| 375 | #define STM32MP1_TZC_ETH_ID U(10) |
| 376 | #define STM32MP1_TZC_DAP_ID U(15) |
| 377 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 378 | #define STM32MP1_FILTER_BIT_ALL U(3) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 379 | |
| 380 | /******************************************************************************* |
| 381 | * STM32MP1 SDMMC |
| 382 | ******************************************************************************/ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 383 | #define STM32MP_SDMMC1_BASE U(0x58005000) |
| 384 | #define STM32MP_SDMMC2_BASE U(0x58007000) |
| 385 | #define STM32MP_SDMMC3_BASE U(0x48004000) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 386 | |
Yann Gautier | 4baf582 | 2019-05-09 13:25:52 +0200 | [diff] [blame] | 387 | #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ |
| 388 | #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ |
| 389 | #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ |
| 390 | #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ |
| 391 | #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 392 | |
| 393 | /******************************************************************************* |
Yann Gautier | 36a1e4b | 2019-01-17 14:52:47 +0100 | [diff] [blame] | 394 | * STM32MP1 BSEC / OTP |
| 395 | ******************************************************************************/ |
| 396 | #define STM32MP1_OTP_MAX_ID 0x5FU |
| 397 | #define STM32MP1_UPPER_OTP_START 0x20U |
| 398 | |
| 399 | #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) |
| 400 | |
| 401 | /* OTP offsets */ |
| 402 | #define DATA0_OTP U(0) |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 403 | #define PART_NUMBER_OTP U(1) |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 404 | #define NAND_OTP U(9) |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 405 | #define PACKAGE_OTP U(16) |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 406 | #define HW2_OTP U(18) |
Yann Gautier | 36a1e4b | 2019-01-17 14:52:47 +0100 | [diff] [blame] | 407 | |
| 408 | /* OTP mask */ |
| 409 | /* DATA0 */ |
| 410 | #define DATA0_OTP_SECURED BIT(6) |
| 411 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 412 | /* PART NUMBER */ |
| 413 | #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) |
| 414 | #define PART_NUMBER_OTP_PART_SHIFT 0 |
| 415 | |
| 416 | /* PACKAGE */ |
| 417 | #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) |
| 418 | #define PACKAGE_OTP_PKG_SHIFT 27 |
| 419 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 420 | /* IWDG OTP */ |
| 421 | #define HW2_OTP_IWDG_HW_POS U(3) |
| 422 | #define HW2_OTP_IWDG_FZ_STOP_POS U(5) |
| 423 | #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) |
| 424 | |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 425 | /* HW2 OTP */ |
| 426 | #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) |
| 427 | |
Lionel Debieve | 402a46b | 2019-11-04 12:28:15 +0100 | [diff] [blame] | 428 | /* NAND OTP */ |
| 429 | /* NAND parameter storage flag */ |
| 430 | #define NAND_PARAM_STORED_IN_OTP BIT(31) |
| 431 | |
| 432 | /* NAND page size in bytes */ |
| 433 | #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) |
| 434 | #define NAND_PAGE_SIZE_SHIFT 29 |
| 435 | #define NAND_PAGE_SIZE_2K U(0) |
| 436 | #define NAND_PAGE_SIZE_4K U(1) |
| 437 | #define NAND_PAGE_SIZE_8K U(2) |
| 438 | |
| 439 | /* NAND block size in pages */ |
| 440 | #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) |
| 441 | #define NAND_BLOCK_SIZE_SHIFT 27 |
| 442 | #define NAND_BLOCK_SIZE_64_PAGES U(0) |
| 443 | #define NAND_BLOCK_SIZE_128_PAGES U(1) |
| 444 | #define NAND_BLOCK_SIZE_256_PAGES U(2) |
| 445 | |
| 446 | /* NAND number of block (in unit of 256 blocs) */ |
| 447 | #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) |
| 448 | #define NAND_BLOCK_NB_SHIFT 19 |
| 449 | #define NAND_BLOCK_NB_UNIT U(256) |
| 450 | |
| 451 | /* NAND bus width in bits */ |
| 452 | #define NAND_WIDTH_MASK BIT(18) |
| 453 | #define NAND_WIDTH_SHIFT 18 |
| 454 | |
| 455 | /* NAND number of ECC bits per 512 bytes */ |
| 456 | #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) |
| 457 | #define NAND_ECC_BIT_NB_SHIFT 15 |
| 458 | #define NAND_ECC_BIT_NB_UNSET U(0) |
| 459 | #define NAND_ECC_BIT_NB_1_BITS U(1) |
| 460 | #define NAND_ECC_BIT_NB_4_BITS U(2) |
| 461 | #define NAND_ECC_BIT_NB_8_BITS U(3) |
| 462 | #define NAND_ECC_ON_DIE U(4) |
| 463 | |
Lionel Debieve | 186b046 | 2019-09-24 18:30:12 +0200 | [diff] [blame] | 464 | /* NAND number of planes */ |
| 465 | #define NAND_PLANE_BIT_NB_MASK BIT(14) |
| 466 | |
Yann Gautier | 36a1e4b | 2019-01-17 14:52:47 +0100 | [diff] [blame] | 467 | /******************************************************************************* |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 468 | * STM32MP1 TAMP |
| 469 | ******************************************************************************/ |
| 470 | #define TAMP_BASE U(0x5C00A000) |
| 471 | #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) |
| 472 | |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 473 | #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 474 | static inline uint32_t tamp_bkpr(uint32_t idx) |
| 475 | { |
| 476 | return TAMP_BKP_REGISTER_BASE + (idx << 2); |
| 477 | } |
| 478 | #endif |
| 479 | |
| 480 | /******************************************************************************* |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 481 | * STM32MP1 DDRCTRL |
| 482 | ******************************************************************************/ |
| 483 | #define DDRCTRL_BASE U(0x5A003000) |
| 484 | |
| 485 | /******************************************************************************* |
| 486 | * STM32MP1 DDRPHYC |
| 487 | ******************************************************************************/ |
| 488 | #define DDRPHYC_BASE U(0x5A004000) |
| 489 | |
| 490 | /******************************************************************************* |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 491 | * STM32MP1 IWDG |
| 492 | ******************************************************************************/ |
| 493 | #define IWDG_MAX_INSTANCE U(2) |
| 494 | #define IWDG1_INST U(0) |
| 495 | #define IWDG2_INST U(1) |
| 496 | |
| 497 | #define IWDG1_BASE U(0x5C003000) |
| 498 | #define IWDG2_BASE U(0x5A002000) |
| 499 | |
| 500 | /******************************************************************************* |
Etienne Carriere | 0cfbff9 | 2020-05-13 10:16:21 +0200 | [diff] [blame] | 501 | * Miscellaneous STM32MP1 peripherals base address |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 502 | ******************************************************************************/ |
Etienne Carriere | 0cfbff9 | 2020-05-13 10:16:21 +0200 | [diff] [blame] | 503 | #define CRYP1_BASE U(0x54001000) |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 504 | #define DBGMCU_BASE U(0x50081000) |
Etienne Carriere | 0cfbff9 | 2020-05-13 10:16:21 +0200 | [diff] [blame] | 505 | #define HASH1_BASE U(0x54002000) |
| 506 | #define I2C4_BASE U(0x5C002000) |
| 507 | #define I2C6_BASE U(0x5c009000) |
| 508 | #define RNG1_BASE U(0x54003000) |
| 509 | #define RTC_BASE U(0x5c004000) |
| 510 | #define SPI6_BASE U(0x5c001000) |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 511 | |
| 512 | /******************************************************************************* |
Yann Gautier | 4d42947 | 2019-02-14 11:15:20 +0100 | [diff] [blame] | 513 | * Device Tree defines |
| 514 | ******************************************************************************/ |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 515 | #define DT_BSEC_COMPAT "st,stm32mp15-bsec" |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 516 | #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 517 | #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" |
Yann Gautier | 4d42947 | 2019-02-14 11:15:20 +0100 | [diff] [blame] | 518 | #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 519 | #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" |
Yann Gautier | 4d42947 | 2019-02-14 11:15:20 +0100 | [diff] [blame] | 520 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 521 | #endif /* STM32MP1_DEF_H */ |