Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | 05fdb83 | 2018-10-25 16:53:04 +0100 | [diff] [blame] | 6 | #ifndef PLAT_ARM_H |
| 7 | #define PLAT_ARM_H |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 8 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 9 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <drivers/arm/tzc_common.h> |
| 12 | #include <lib/bakery_lock.h> |
| 13 | #include <lib/cassert.h> |
| 14 | #include <lib/el3_runtime/cpu_data.h> |
| 15 | #include <lib/spinlock.h> |
| 16 | #include <lib/utils_def.h> |
| 17 | #include <lib/xlat_tables/xlat_tables_compat.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 18 | |
Sandrine Bailleux | f402a52 | 2016-09-15 10:09:53 +0100 | [diff] [blame] | 19 | /******************************************************************************* |
| 20 | * Forward declarations |
| 21 | ******************************************************************************/ |
Sandrine Bailleux | f402a52 | 2016-09-15 10:09:53 +0100 | [diff] [blame] | 22 | struct meminfo; |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 23 | struct image_info; |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 24 | struct bl_params; |
Sandrine Bailleux | f402a52 | 2016-09-15 10:09:53 +0100 | [diff] [blame] | 25 | |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 26 | typedef struct arm_tzc_regions_info { |
| 27 | unsigned long long base; |
| 28 | unsigned long long end; |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 29 | unsigned int sec_attr; |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 30 | unsigned int nsaid_permissions; |
| 31 | } arm_tzc_regions_info_t; |
| 32 | |
| 33 | /******************************************************************************* |
| 34 | * Default mapping definition of the TrustZone Controller for ARM standard |
| 35 | * platforms. |
| 36 | * Configure: |
| 37 | * - Region 0 with no access; |
| 38 | * - Region 1 with secure access only; |
| 39 | * - the remaining DRAM regions access from the given Non-Secure masters. |
| 40 | ******************************************************************************/ |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 41 | #if SPM_MM |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 42 | #define ARM_TZC_REGIONS_DEF \ |
| 43 | {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ |
| 44 | TZC_REGION_S_RDWR, 0}, \ |
| 45 | {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 46 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 47 | {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 48 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 49 | {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 50 | PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 51 | PLAT_ARM_TZC_NS_DEV_ACCESS} |
| 52 | |
| 53 | #else |
| 54 | #define ARM_TZC_REGIONS_DEF \ |
| 55 | {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ |
| 56 | TZC_REGION_S_RDWR, 0}, \ |
| 57 | {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 58 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 59 | {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 60 | PLAT_ARM_TZC_NS_DEV_ACCESS} |
| 61 | #endif |
| 62 | |
Chris Kay | 2b54c0c | 2018-05-09 15:46:07 +0100 | [diff] [blame] | 63 | #define ARM_CASSERT_MMAP \ |
| 64 | CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ |
| 65 | assert_plat_arm_mmap_mismatch); \ |
| 66 | CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ |
| 67 | <= MAX_MMAP_REGIONS, \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 68 | assert_max_mmap_regions); |
| 69 | |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 70 | void arm_setup_romlib(void); |
| 71 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 72 | #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 73 | /* |
| 74 | * Use this macro to instantiate lock before it is used in below |
| 75 | * arm_lock_xxx() macros |
| 76 | */ |
Sandrine Bailleux | ceb258e | 2018-07-11 13:59:18 +0200 | [diff] [blame] | 77 | #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 78 | #define ARM_LOCK_GET_INSTANCE (&arm_lock) |
Roberto Vargas | 0099694 | 2017-11-13 13:41:58 +0000 | [diff] [blame] | 79 | |
| 80 | #if !HW_ASSISTED_COHERENCY |
| 81 | #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) |
| 82 | #else |
| 83 | #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock |
| 84 | #endif |
| 85 | #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) |
| 86 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 87 | /* |
| 88 | * These are wrapper macros to the Coherent Memory Bakery Lock API. |
| 89 | */ |
| 90 | #define arm_lock_init() bakery_lock_init(&arm_lock) |
| 91 | #define arm_lock_get() bakery_lock_get(&arm_lock) |
| 92 | #define arm_lock_release() bakery_lock_release(&arm_lock) |
| 93 | |
| 94 | #else |
| 95 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 96 | /* |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 97 | * Empty macros for all other BL stages other than BL31 and BL32 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 98 | */ |
Jeenu Viswambharan | 749d25b | 2017-08-23 14:12:59 +0100 | [diff] [blame] | 99 | #define ARM_INSTANTIATE_LOCK static int arm_lock __unused |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 100 | #define ARM_LOCK_GET_INSTANCE 0 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 101 | #define arm_lock_init() |
| 102 | #define arm_lock_get() |
| 103 | #define arm_lock_release() |
| 104 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 105 | #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 106 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 107 | #if ARM_RECOM_STATE_ID_ENC |
| 108 | /* |
| 109 | * Macros used to parse state information from State-ID if it is using the |
| 110 | * recommended encoding for State-ID. |
| 111 | */ |
| 112 | #define ARM_LOCAL_PSTATE_WIDTH 4 |
| 113 | #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) |
| 114 | |
| 115 | /* Macros to construct the composite power state */ |
| 116 | |
| 117 | /* Make composite power state parameter till power level 0 */ |
| 118 | #if PSCI_EXTENDED_STATE_ID |
| 119 | |
| 120 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 121 | (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) |
| 122 | #else |
| 123 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 124 | (((lvl0_state) << PSTATE_ID_SHIFT) | \ |
| 125 | ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ |
| 126 | ((type) << PSTATE_TYPE_SHIFT)) |
| 127 | #endif /* __PSCI_EXTENDED_STATE_ID__ */ |
| 128 | |
| 129 | /* Make composite power state parameter till power level 1 */ |
| 130 | #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 131 | (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ |
| 132 | arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) |
| 133 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 134 | /* Make composite power state parameter till power level 2 */ |
| 135 | #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 136 | (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ |
| 137 | arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) |
| 138 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 139 | #endif /* __ARM_RECOM_STATE_ID_ENC__ */ |
| 140 | |
Jeenu Viswambharan | bc1a929 | 2017-02-16 14:55:15 +0000 | [diff] [blame] | 141 | /* ARM State switch error codes */ |
| 142 | #define STATE_SW_E_PARAM (-2) |
| 143 | #define STATE_SW_E_DENIED (-3) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 144 | |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 145 | /* plat_get_rotpk_info() flags */ |
| 146 | #define ARM_ROTPK_REGS_ID 1 |
| 147 | #define ARM_ROTPK_DEVEL_RSA_ID 2 |
| 148 | #define ARM_ROTPK_DEVEL_ECDSA_ID 3 |
| 149 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 150 | /* IO storage utility functions */ |
| 151 | void arm_io_setup(void); |
| 152 | |
| 153 | /* Security utility functions */ |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 154 | void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 155 | struct tzc_dmc500_driver_data; |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 156 | void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, |
| 157 | const arm_tzc_regions_info_t *tzc_regions); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 158 | |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 159 | /* Console utility functions */ |
| 160 | void arm_console_boot_init(void); |
| 161 | void arm_console_boot_end(void); |
| 162 | void arm_console_runtime_init(void); |
| 163 | void arm_console_runtime_end(void); |
| 164 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 165 | /* Systimer utility function */ |
| 166 | void arm_configure_sys_timer(void); |
| 167 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 168 | /* PM utility functions */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 169 | int arm_validate_power_state(unsigned int power_state, |
| 170 | psci_power_state_t *req_state); |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 171 | int arm_validate_psci_entrypoint(uintptr_t entrypoint); |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 172 | int arm_validate_ns_entrypoint(uintptr_t entrypoint); |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 173 | void arm_system_pwr_domain_save(void); |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 174 | void arm_system_pwr_domain_resume(void); |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 175 | int arm_psci_read_mem_protect(int *enabled); |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 176 | int arm_nor_psci_write_mem_protect(int val); |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 177 | void arm_nor_psci_do_static_mem_protect(void); |
| 178 | void arm_nor_psci_do_dyn_mem_protect(void); |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 179 | int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 180 | |
| 181 | /* Topology utility function */ |
| 182 | int arm_check_mpidr(u_register_t mpidr); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 183 | |
| 184 | /* BL1 utility functions */ |
| 185 | void arm_bl1_early_platform_setup(void); |
| 186 | void arm_bl1_platform_setup(void); |
| 187 | void arm_bl1_plat_arch_setup(void); |
| 188 | |
| 189 | /* BL2 utility functions */ |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 190 | void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 191 | void arm_bl2_platform_setup(void); |
| 192 | void arm_bl2_plat_arch_setup(void); |
| 193 | uint32_t arm_get_spsr_for_bl32_entry(void); |
| 194 | uint32_t arm_get_spsr_for_bl33_entry(void); |
Ambroise Vincent | b237bca | 2019-02-13 15:58:00 +0000 | [diff] [blame] | 195 | int arm_bl2_plat_handle_post_image_load(unsigned int image_id); |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 196 | int arm_bl2_handle_post_image_load(unsigned int image_id); |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 197 | struct bl_params *arm_get_next_bl_params(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 198 | |
Roberto Vargas | 5220780 | 2017-11-17 13:22:18 +0000 | [diff] [blame] | 199 | /* BL2 at EL3 functions */ |
| 200 | void arm_bl2_el3_early_platform_setup(void); |
| 201 | void arm_bl2_el3_plat_arch_setup(void); |
| 202 | |
Yatharth Kochar | 3a11eda | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 203 | /* BL2U utility functions */ |
| 204 | void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, |
| 205 | void *plat_info); |
| 206 | void arm_bl2u_platform_setup(void); |
| 207 | void arm_bl2u_plat_arch_setup(void); |
| 208 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 209 | /* BL31 utility functions */ |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 210 | void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, |
| 211 | uintptr_t hw_config, void *plat_params_from_bl2); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 212 | void arm_bl31_platform_setup(void); |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 213 | void arm_bl31_plat_runtime_setup(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 214 | void arm_bl31_plat_arch_setup(void); |
| 215 | |
| 216 | /* TSP utility functions */ |
| 217 | void arm_tsp_early_platform_setup(void); |
| 218 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 219 | /* SP_MIN utility functions */ |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 220 | void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, |
| 221 | uintptr_t hw_config, void *plat_params_from_bl2); |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 222 | void arm_sp_min_plat_runtime_setup(void); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 223 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 224 | /* FIP TOC validity check */ |
| 225 | int arm_io_is_toc_valid(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 226 | |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 227 | /* Utility functions for Dynamic Config */ |
| 228 | void arm_load_tb_fw_config(void); |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 229 | void arm_bl2_set_tb_cfg_addr(void *dtb); |
| 230 | void arm_bl2_dyn_cfg_init(void); |
John Tsichritzis | c34341a | 2018-07-30 13:41:52 +0100 | [diff] [blame] | 231 | void arm_bl1_set_mbedtls_heap(void); |
| 232 | int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 233 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 234 | /* |
Daniel Boulby | b1b058d | 2018-09-18 11:52:49 +0100 | [diff] [blame] | 235 | * Free the memory storing initialization code only used during an images boot |
| 236 | * time so it can be reclaimed for runtime data |
| 237 | */ |
| 238 | void arm_free_init_memory(void); |
| 239 | |
| 240 | /* |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 241 | * Mandatory functions required in ARM standard platforms |
| 242 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 243 | unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 244 | void plat_arm_gic_driver_init(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 245 | void plat_arm_gic_init(void); |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 246 | void plat_arm_gic_cpuif_enable(void); |
| 247 | void plat_arm_gic_cpuif_disable(void); |
Jeenu Viswambharan | 78132c9 | 2016-12-09 11:12:34 +0000 | [diff] [blame] | 248 | void plat_arm_gic_redistif_on(void); |
| 249 | void plat_arm_gic_redistif_off(void); |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 250 | void plat_arm_gic_pcpu_init(void); |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 251 | void plat_arm_gic_save(void); |
| 252 | void plat_arm_gic_resume(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 253 | void plat_arm_security_setup(void); |
| 254 | void plat_arm_pwrc_setup(void); |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 255 | void plat_arm_interconnect_init(void); |
| 256 | void plat_arm_interconnect_enter_coherency(void); |
| 257 | void plat_arm_interconnect_exit_coherency(void); |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 258 | void plat_arm_program_trusted_mailbox(uintptr_t address); |
Sathees Balya | 2257607 | 2018-09-03 17:41:13 +0100 | [diff] [blame] | 259 | int plat_arm_bl1_fwu_needed(void); |
Ambroise Vincent | fa42c9e | 2019-07-04 14:58:45 +0100 | [diff] [blame] | 260 | __dead2 void plat_arm_error_handler(int err); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 261 | |
Vijayenthiran Subramaniam | 2dfa764 | 2019-10-11 14:01:25 +0530 | [diff] [blame] | 262 | /* |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 263 | * Optional functions in ARM standard platforms |
Vijayenthiran Subramaniam | 2dfa764 | 2019-10-11 14:01:25 +0530 | [diff] [blame] | 264 | */ |
| 265 | void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 266 | int arm_get_rotpk_info(void **key_ptr, unsigned int *key_len, |
| 267 | unsigned int *flags); |
| 268 | int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, |
| 269 | unsigned int *flags); |
| 270 | int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, |
| 271 | unsigned int *flags); |
| 272 | int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, |
| 273 | unsigned int *flags); |
Vijayenthiran Subramaniam | 2dfa764 | 2019-10-11 14:01:25 +0530 | [diff] [blame] | 274 | |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 275 | #if ARM_PLAT_MT |
| 276 | unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); |
| 277 | #endif |
| 278 | |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 279 | /* |
| 280 | * This function is called after loading SCP_BL2 image and it is used to perform |
| 281 | * any platform-specific actions required to handle the SCP firmware. |
| 282 | */ |
| 283 | int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 284 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 285 | /* |
| 286 | * Optional functions required in ARM standard platforms |
| 287 | */ |
| 288 | void plat_arm_io_setup(void); |
| 289 | int plat_arm_get_alt_image_source( |
Juan Castillo | 3a66aca | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 290 | unsigned int image_id, |
| 291 | uintptr_t *dev_handle, |
| 292 | uintptr_t *image_spec); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 293 | unsigned int plat_arm_calc_core_pos(u_register_t mpidr); |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 294 | const mmap_region_t *plat_arm_get_mmap(void); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 295 | |
Soby Mathew | 0b4c5a3 | 2016-10-21 17:51:22 +0100 | [diff] [blame] | 296 | /* Allow platform to override psci_pm_ops during runtime */ |
| 297 | const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); |
| 298 | |
Jeenu Viswambharan | bc1a929 | 2017-02-16 14:55:15 +0000 | [diff] [blame] | 299 | /* Execution state switch in ARM platforms */ |
| 300 | int arm_execution_state_switch(unsigned int smc_fid, |
| 301 | uint32_t pc_hi, |
| 302 | uint32_t pc_lo, |
| 303 | uint32_t cookie_hi, |
| 304 | uint32_t cookie_lo, |
| 305 | void *handle); |
| 306 | |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 307 | /* Optional functions for SP_MIN */ |
| 308 | void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, |
| 309 | u_register_t arg2, u_register_t arg3); |
| 310 | |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 311 | /* global variables */ |
| 312 | extern plat_psci_ops_t plat_arm_psci_pm_ops; |
| 313 | extern const mmap_region_t plat_arm_mmap[]; |
Jeenu Viswambharan | 4542cfe | 2018-07-19 08:03:46 +0100 | [diff] [blame] | 314 | extern const unsigned int arm_pm_idle_states[]; |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 315 | |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 316 | /* secure watchdog */ |
| 317 | void plat_arm_secure_wdt_start(void); |
| 318 | void plat_arm_secure_wdt_stop(void); |
| 319 | |
Antonio Nino Diaz | 05fdb83 | 2018-10-25 16:53:04 +0100 | [diff] [blame] | 320 | #endif /* PLAT_ARM_H */ |