blob: 5bd4276669293b5ab6a1adce8cb0670d8a997acb [file] [log] [blame]
developer8670d252021-03-19 22:13:11 +08001#
2# Copyright (c) 2021, MediaTek Inc. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7MTK_PLAT := plat/mediatek
8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
9
10PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
christine.zhua22c10b2021-03-24 21:44:52 +080011 -I${MTK_PLAT}/common/drivers/gic600/ \
developer4c1354b2021-04-22 14:56:58 +080012 -I${MTK_PLAT}/common/drivers/timer/ \
developer2a56b2c2020-06-16 13:28:28 +080013 -I${MTK_PLAT_SOC}/drivers/spmc/ \
developer8670d252021-03-19 22:13:11 +080014 -I${MTK_PLAT_SOC}/include/
15
christine.zhua22c10b2021-03-24 21:44:52 +080016GICV3_SUPPORT_GIC600 := 1
developer8670d252021-03-19 22:13:11 +080017include drivers/arm/gic/v3/gicv3.mk
18include lib/xlat_tables_v2/xlat_tables.mk
19
20PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \
21 ${XLAT_TABLES_LIB_SRCS} \
22 plat/common/aarch64/crash_console_helpers.S \
23 plat/common/plat_psci_common.c
24
25
26BL31_SOURCES += common/desc_image_load.c \
developer98b97182021-03-26 18:33:43 +080027 drivers/delay_timer/delay_timer.c \
28 drivers/delay_timer/generic_delay_timer.c \
developer8670d252021-03-19 22:13:11 +080029 drivers/ti/uart/aarch64/16550_console.S \
30 lib/bl_aux_params/bl_aux_params.c \
31 lib/cpus/aarch64/cortex_a55.S \
32 lib/cpus/aarch64/cortex_a78.S \
33 plat/common/plat_gicv3.c \
christine.zhua22c10b2021-03-24 21:44:52 +080034 ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
developer4c1354b2021-04-22 14:56:58 +080035 ${MTK_PLAT}/common/drivers/timer/mt_timer.c \
developer8273a602021-03-25 11:26:46 +080036 ${MTK_PLAT}/common/mtk_cirq.c \
developer8670d252021-03-19 22:13:11 +080037 ${MTK_PLAT}/common/mtk_plat_common.c \
38 ${MTK_PLAT}/common/params_setup.c \
39 ${MTK_PLAT_SOC}/aarch64/platform_common.c \
40 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
41 ${MTK_PLAT_SOC}/bl31_plat_setup.c \
developer2a56b2c2020-06-16 13:28:28 +080042 ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
developer8670d252021-03-19 22:13:11 +080043 ${MTK_PLAT_SOC}/plat_pm.c \
44 ${MTK_PLAT_SOC}/plat_topology.c
45
46# Configs for A78 and A55
47HW_ASSISTED_COHERENCY := 1
48USE_COHERENT_MEM := 0
49CTX_INCLUDE_AARCH32_REGS := 0
50ERRATA_A55_1530923 := 1
51
52# indicate the reset vector address can be programmed
53PROGRAMMABLE_RESET_ADDRESS := 1
54
55COLD_BOOT_SINGLE_CPU := 1
56
57MACH_MT8195 := 1
58$(eval $(call add_define,MACH_MT8195))
59
60include lib/coreboot/coreboot.mk