blob: 35d2c480f34adf5efb812ca9a4146cf4af63d5b1 [file] [log] [blame]
Jimmy Brisson958a0b12020-09-30 15:28:03 -05001/*
Sona Mathewfe405d02023-01-11 17:04:24 -06002 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Jimmy Brisson958a0b12020-09-30 15:28:03 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_v1.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
Bipin Ravi86499742022-01-18 01:59:06 -060013#include "wa_cve_2022_23960_bhb_vector.S"
Jimmy Brisson958a0b12020-09-30 15:28:03 -050014
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
Bipin Ravi86499742022-01-18 01:59:06 -060025#if WORKAROUND_CVE_2022_23960
26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
27#endif /* WORKAROUND_CVE_2022_23960 */
28
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050029workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
Juan Pablo Conde31c93372022-02-28 14:14:44 -050030 /* Inserts a DMB SY before and after MRS PAR_EL1 */
31 ldr x0, =0x0
32 msr NEOVERSE_V1_CPUPSELR_EL3, x0
33 ldr x0, = 0xEE070F14
34 msr NEOVERSE_V1_CPUPOR_EL3, x0
35 ldr x0, = 0xFFFF0FFF
36 msr NEOVERSE_V1_CPUPMR_EL3, x0
37 ldr x0, =0x4005027FF
38 msr NEOVERSE_V1_CPUPCR_EL3, x0
39
40 /* Inserts a DMB SY before STREX imm offset */
41 ldr x0, =0x1
42 msr NEOVERSE_V1_CPUPSELR_EL3, x0
43 ldr x0, =0x00e8400000
44 msr NEOVERSE_V1_CPUPOR_EL3, x0
45 ldr x0, =0x00fff00000
46 msr NEOVERSE_V1_CPUPMR_EL3, x0
47 ldr x0, = 0x4001027FF
48 msr NEOVERSE_V1_CPUPCR_EL3, x0
49
50 /* Inserts a DMB SY before STREX[BHD}/STLEX* */
51 ldr x0, =0x2
52 msr NEOVERSE_V1_CPUPSELR_EL3, x0
53 ldr x0, =0x00e8c00040
54 msr NEOVERSE_V1_CPUPOR_EL3, x0
55 ldr x0, =0x00fff00040
56 msr NEOVERSE_V1_CPUPMR_EL3, x0
57 ldr x0, = 0x4001027FF
58 msr NEOVERSE_V1_CPUPCR_EL3, x0
59
60 /* Inserts a DMB SY after STREX imm offset */
61 ldr x0, =0x3
62 msr NEOVERSE_V1_CPUPSELR_EL3, x0
63 ldr x0, =0x00e8400000
64 msr NEOVERSE_V1_CPUPOR_EL3, x0
65 ldr x0, =0x00fff00000
66 msr NEOVERSE_V1_CPUPMR_EL3, x0
67 ldr x0, = 0x4004027FF
68 msr NEOVERSE_V1_CPUPCR_EL3, x0
69
70 /* Inserts a DMB SY after STREX[BHD}/STLEX* */
71 ldr x0, =0x4
72 msr NEOVERSE_V1_CPUPSELR_EL3, x0
73 ldr x0, =0x00e8c00040
74 msr NEOVERSE_V1_CPUPOR_EL3, x0
75 ldr x0, =0x00fff00040
76 msr NEOVERSE_V1_CPUPMR_EL3, x0
77 ldr x0, = 0x4004027FF
78 msr NEOVERSE_V1_CPUPCR_EL3, x0
79
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050080workaround_reset_end neoverse_v1, ERRATUM(1618635)
Juan Pablo Conde31c93372022-02-28 14:14:44 -050081
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050082check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0)
laurenw-arm3c86d832021-08-02 13:22:32 -050083
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050084workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420
laurenw-arm3c86d832021-08-02 13:22:32 -050085 /* Set bit 53 in CPUECTLR_EL1 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -050086 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050087workaround_reset_end neoverse_v1, ERRATUM(1774420)
laurenw-arm3c86d832021-08-02 13:22:32 -050088
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050089check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0)
laurenw-arm3c86d832021-08-02 13:22:32 -050090
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050091workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573
johpow01c73b03c2021-05-03 15:33:39 -050092 /* Set bit 2 in ACTLR2_EL1 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -050093 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050094workaround_reset_end neoverse_v1, ERRATUM(1791573)
johpow01c73b03c2021-05-03 15:33:39 -050095
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050096check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0)
johpow01c73b03c2021-05-03 15:33:39 -050097
Arvind Ram Prakash48bda112023-07-20 17:11:11 -050098workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267
laurenw-armb1923e92021-08-02 14:40:08 -050099 /* Set bit 28 in ACTLR2_EL1 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500100 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500101workaround_reset_end neoverse_v1, ERRATUM(1852267)
laurenw-armb1923e92021-08-02 14:40:08 -0500102
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500103check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0)
laurenw-armb1923e92021-08-02 14:40:08 -0500104
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500105workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756
laurenw-arm6b56f962021-08-02 15:00:15 -0500106 /* Set bit 8 in CPUECTLR_EL1 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500107 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500108workaround_reset_end neoverse_v1, ERRATUM(1925756)
laurenw-arm6b56f962021-08-02 15:00:15 -0500109
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500110check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1)
laurenw-arm6b56f962021-08-02 15:00:15 -0500111
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500112workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577
johpow0107acb4f2020-10-07 16:38:37 -0500113 mov x0, #0
114 msr S3_6_C15_C8_0, x0
115 ldr x0, =0x10E3900002
116 msr S3_6_C15_C8_2, x0
117 ldr x0, =0x10FFF00083
118 msr S3_6_C15_C8_3, x0
119 ldr x0, =0x2001003FF
120 msr S3_6_C15_C8_1, x0
121
122 mov x0, #1
123 msr S3_6_C15_C8_0, x0
124 ldr x0, =0x10E3800082
125 msr S3_6_C15_C8_2, x0
126 ldr x0, =0x10FFF00083
127 msr S3_6_C15_C8_3, x0
128 ldr x0, =0x2001003FF
129 msr S3_6_C15_C8_1, x0
130
131 mov x0, #2
132 msr S3_6_C15_C8_0, x0
133 ldr x0, =0x10E3800200
134 msr S3_6_C15_C8_2, x0
135 ldr x0, =0x10FFF003E0
136 msr S3_6_C15_C8_3, x0
137 ldr x0, =0x2001003FF
138 msr S3_6_C15_C8_1, x0
139
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500140workaround_reset_end neoverse_v1, ERRATUM(1940577)
johpow0107acb4f2020-10-07 16:38:37 -0500141
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500142check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1)
johpow0107acb4f2020-10-07 16:38:37 -0500143
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500144workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096
johpow0197db6752021-08-02 18:59:08 -0500145 mov x0, #0x3
146 msr S3_6_C15_C8_0, x0
147 ldr x0, =0xEE010F12
148 msr S3_6_C15_C8_2, x0
149 ldr x0, =0xFFFF0FFF
150 msr S3_6_C15_C8_3, x0
151 ldr x0, =0x80000000003FF
152 msr S3_6_C15_C8_1, x0
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500153workaround_reset_end neoverse_v1, ERRATUM(1966096)
johpow0197db6752021-08-02 18:59:08 -0500154
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500155check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
johpow0197db6752021-08-02 18:59:08 -0500156
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500157workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
Arvind Ram Prakash9fc6f832023-07-18 17:17:44 -0500158 mrs x1, NEOVERSE_V1_CPUECTLR_EL1
159 mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
160 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
161 msr NEOVERSE_V1_CPUECTLR_EL1, x1
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500162workaround_reset_end neoverse_v1, ERRATUM(2108267)
johpow01ad1ca342021-08-03 14:35:20 -0500163
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500164check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 1)
nayanpatel-armfc26ffe2021-09-28 13:41:03 -0700165
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500166workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
Arvind Ram Prakash9fc6f832023-07-18 17:17:44 -0500167 mov x0, #0x3
168 msr S3_6_C15_C8_0, x0
169 ldr x0, =0xEE720F14
170 msr S3_6_C15_C8_2, x0
171 ldr x0, =0xFFFF0FDF
172 msr S3_6_C15_C8_3, x0
173 ldr x0, =0x40000005003FF
174 msr S3_6_C15_C8_1, x0
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500175workaround_reset_end neoverse_v1, ERRATUM(2139242)
nayanpatel-armfc26ffe2021-09-28 13:41:03 -0700176
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500177check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1)
nayanpatel-armfc26ffe2021-09-28 13:41:03 -0700178
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500179workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392
johpow014de29cb2021-09-02 18:29:17 -0500180 ldr x0, =0x5
181 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
182 ldr x0, =0x10F600E000
183 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
184 ldr x0, =0x10FF80E000
185 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
186 ldr x0, =0x80000000003FF
187 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500188workaround_reset_end neoverse_v1, ERRATUM(2216392)
johpow014de29cb2021-09-02 18:29:17 -0500189
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500190check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1)
Bipin Ravi971938f2022-06-08 16:28:46 -0500191
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500192workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
Bipin Ravi971938f2022-06-08 16:28:46 -0500193 /* Set bit 0 in ACTLR2_EL1 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500194 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500195workaround_reset_end neoverse_v1, ERRATUM(2294912)
Bipin Ravi971938f2022-06-08 16:28:46 -0500196
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500197check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 1)
Bipin Ravib4cb31f2022-06-14 17:09:23 -0500198
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500199workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
Bipin Ravib4cb31f2022-06-14 17:09:23 -0500200 /* Set bit 40 in ACTLR2_EL1 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500201 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500202workaround_reset_end neoverse_v1, ERRATUM(2372203)
Bipin Ravib4cb31f2022-06-14 17:09:23 -0500203
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500204check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1)
Bipin Ravife4b0c42022-12-15 11:57:53 -0600205
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500206workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
Bipin Ravife4b0c42022-12-15 11:57:53 -0600207 /* dsb before isb of power down sequence */
208 dsb sy
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500209workaround_runtime_end neoverse_v1, ERRATUM(2743093)
Bipin Ravife4b0c42022-12-15 11:57:53 -0600210
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500211check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2)
Bipin Ravife4b0c42022-12-15 11:57:53 -0600212
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500213workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500214 sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56
215 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500216workaround_reset_end neoverse_v1, ERRATUM(2743233)
Sona Mathew2ef5db72023-03-02 15:07:55 -0600217
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500218check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2)
Sona Mathewfe405d02023-01-11 17:04:24 -0600219
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500220workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500221 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500222workaround_reset_end neoverse_v1, ERRATUM(2779461)
Sona Mathewfe405d02023-01-11 17:04:24 -0600223
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500224check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2)
Sona Mathewfe405d02023-01-11 17:04:24 -0600225
Sona Mathewfe405d02023-01-11 17:04:24 -0600226
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500227workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960
228#if IMAGE_BL31
229 /*
230 * The Neoverse-V1 generic vectors are overridden to apply errata
231 * mitigation on exception entry from lower ELs.
232 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500233 override_vector_table wa_cve_vbar_neoverse_v1
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500234#endif /* IMAGE_BL31 */
235workaround_reset_end neoverse_v1, CVE(2022,23960)
236
237check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
Bipin Ravi86499742022-01-18 01:59:06 -0600238
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500239 /* ---------------------------------------------
240 * HW will do the cache maintenance while powering down
241 * ---------------------------------------------
242 */
243func neoverse_v1_core_pwr_dwn
244 /* ---------------------------------------------
245 * Enable CPU power down bit in power control register
246 * ---------------------------------------------
247 */
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -0500248 sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
249 apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
250
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500251 isb
252 ret
253endfunc neoverse_v1_core_pwr_dwn
254
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500255errata_report_shim neoverse_v1
johpow01c73b03c2021-05-03 15:33:39 -0500256
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500257cpu_reset_func_start neoverse_v1
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500258 /* Disable speculative loads */
259 msr SSBS, xzr
Arvind Ram Prakash48bda112023-07-20 17:11:11 -0500260cpu_reset_func_end neoverse_v1
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500261
262 /* ---------------------------------------------
263 * This function provides Neoverse-V1 specific
264 * register information for crash reporting.
265 * It needs to return with x6 pointing to
266 * a list of register names in ascii and
267 * x8 - x15 having values of registers to be
268 * reported.
269 * ---------------------------------------------
270 */
271.section .rodata.neoverse_v1_regs, "aS"
272neoverse_v1_regs: /* The ascii list of register names to be reported */
273 .asciz "cpuectlr_el1", ""
274
275func neoverse_v1_cpu_reg_dump
276 adr x6, neoverse_v1_regs
277 mrs x8, NEOVERSE_V1_CPUECTLR_EL1
278 ret
279endfunc neoverse_v1_cpu_reg_dump
280
281declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
282 neoverse_v1_reset_func, \
283 neoverse_v1_core_pwr_dwn