refactor(cpus): reorder Neoverse V1 errata by ascending order
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1c531fe166218804e4fc9ebbdeda2bfebdd69081
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 363c2e6..a1a3cc0 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -306,68 +306,68 @@
endfunc check_errata_1966096
/* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2139242.
+ * Errata Workaround for Neoverse V1 Errata #2108267.
* This applies to revisions r0p0, r1p0, and r1p1, it
* is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
+ * Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
-func errata_neoverse_v1_2139242_wa
+func errata_neoverse_v1_2108267_wa
/* Check workaround compatibility. */
mov x17, x30
- bl check_errata_2139242
+ bl check_errata_2108267
cbz x0, 1f
/* Apply the workaround. */
- mov x0, #0x3
- msr S3_6_C15_C8_0, x0
- ldr x0, =0xEE720F14
- msr S3_6_C15_C8_2, x0
- ldr x0, =0xFFFF0FDF
- msr S3_6_C15_C8_3, x0
- ldr x0, =0x40000005003FF
- msr S3_6_C15_C8_1, x0
- isb
-
+ mrs x1, NEOVERSE_V1_CPUECTLR_EL1
+ mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_V1_CPUECTLR_EL1, x1
1:
ret x17
-endfunc errata_neoverse_v1_2139242_wa
+endfunc errata_neoverse_v1_2108267_wa
-func check_errata_2139242
+func check_errata_2108267
/* Applies to r0p0, r1p0, r1p1 */
mov x1, #0x11
b cpu_rev_var_ls
-endfunc check_errata_2139242
+endfunc check_errata_2108267
/* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2108267.
+ * Errata Workaround for Neoverse V1 Errata #2139242.
* This applies to revisions r0p0, r1p0, and r1p1, it
* is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
+ * Shall clobber: x0-x17
* --------------------------------------------------
*/
-func errata_neoverse_v1_2108267_wa
+func errata_neoverse_v1_2139242_wa
/* Check workaround compatibility. */
mov x17, x30
- bl check_errata_2108267
+ bl check_errata_2139242
cbz x0, 1f
/* Apply the workaround. */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
+ mov x0, #0x3
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0xEE720F14
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0xFFFF0FDF
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x40000005003FF
+ msr S3_6_C15_C8_1, x0
+ isb
+
1:
ret x17
-endfunc errata_neoverse_v1_2108267_wa
+endfunc errata_neoverse_v1_2139242_wa
-func check_errata_2108267
+func check_errata_2139242
/* Applies to r0p0, r1p0, r1p1 */
mov x1, #0x11
b cpu_rev_var_ls
-endfunc check_errata_2108267
+endfunc check_errata_2139242
/* --------------------------------------------------
* Errata Workaround for Neoverse V1 Errata #2216392.