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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Dan Handley6fa89a22018-02-27 16:03:58 +00002# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000022# ARM Architecture major and minor versions: 8.0 by default.
23ARM_ARCH_MAJOR := 8
24ARM_ARCH_MINOR := 0
25
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010026# Base commit to perform code check on
27BASE_COMMIT := origin/master
28
Roberto Vargase0e99462017-10-30 14:43:43 +000029# Execute BL2 at EL3
30BL2_AT_EL3 := 0
31
Jiafei Pan43a7bf42018-03-21 07:20:09 +000032# BL2 image is stored in XIP memory, for now, this option is only supported
33# when BL2_AT_EL3 is 1.
34BL2_IN_XIP_MEM := 0
35
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010036# By default, consider that the platform may release several CPUs out of reset.
37# The platform Makefile is free to override this value.
38COLD_BOOT_SINGLE_CPU := 0
39
Julius Wernerb624ae02017-06-09 15:17:15 -070040# Flag to compile in coreboot support code. Exclude by default. The coreboot
41# Makefile system will set this when compiling TF as part of a coreboot image.
42COREBOOT := 0
43
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010044# For Chain of Trust
45CREATE_KEYS := 1
46
47# Build flag to include AArch32 registers in cpu context save and restore during
48# world switch. This flag must be set to 0 for AArch64-only platforms.
49CTX_INCLUDE_AARCH32_REGS := 1
50
51# Include FP registers in cpu context
52CTX_INCLUDE_FPREGS := 0
53
54# Debug build
55DEBUG := 0
56
57# Build platform
58DEFAULT_PLAT := fvp
59
Soby Mathew9fe88042018-03-26 12:43:37 +010060# Enable capability to disable authentication dynamically. Only meant for
61# development platforms.
62DYN_DISABLE_AUTH := 0
63
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010064# Build option to enable MPAM for lower ELs
65ENABLE_MPAM_FOR_LOWER_ELS := 0
66
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010067# Flag to enable Performance Measurement Framework
68ENABLE_PMF := 0
69
70# Flag to enable PSCI STATs functionality
71ENABLE_PSCI_STAT := 0
72
73# Flag to enable runtime instrumentation using PMF
74ENABLE_RUNTIME_INSTRUMENTATION := 0
75
Douglas Raillard306593d2017-02-24 18:14:15 +000076# Flag to enable stack corruption protection
77ENABLE_STACK_PROTECTOR := 0
78
Jeenu Viswambharan10a67272017-09-22 08:32:10 +010079# Flag to enable exception handling in EL3
80EL3_EXCEPTION_HANDLING := 0
81
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010082# Build flag to treat usage of deprecated platform and framework APIs as error.
83ERROR_DEPRECATED := 0
84
Jeenu Viswambharanf00da742017-12-08 12:13:51 +000085# Fault injection support
86FAULT_INJECTION_SUPPORT := 0
87
Masahiro Yamada4d87eb42016-12-25 13:52:22 +090088# Byte alignment that each component in FIP is aligned to
89FIP_ALIGN := 0
90
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010091# Default FIP file name
92FIP_NAME := fip.bin
93
94# Default FWU_FIP file name
95FWU_FIP_NAME := fwu_fip.bin
96
97# For Chain of Trust
98GENERATE_COT := 0
99
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100100# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
101# default, they are for Secure EL1.
102GICV2_G0_FOR_EL3 := 0
103
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000104# Route External Aborts to EL3. Disabled by default; External Aborts are handled
105# by lower ELs.
106HANDLE_EA_EL3_FIRST := 0
107
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000108# Whether system coherency is managed in hardware, without explicit software
109# operations.
110HW_ASSISTED_COHERENCY := 0
111
Soby Mathew13b16052017-08-31 11:49:32 +0100112# Set the default algorithm for the generation of Trusted Board Boot keys
113KEY_ALG := rsa
114
Dan Handley6fa89a22018-02-27 16:03:58 +0000115# Enable use of the console API allowing multiple consoles to be registered
116# at the same time.
117MULTI_CONSOLE_API := 0
Julius Werner94f89072017-07-31 18:15:11 -0700118
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100119# NS timer register save and restore
120NS_TIMER_SWITCH := 0
121
122# Build PL011 UART driver in minimal generic UART mode
123PL011_GENERIC_UART := 0
124
125# By default, consider that the platform's reset address is not programmable.
126# The platform Makefile is free to override this value.
127PROGRAMMABLE_RESET_ADDRESS := 0
128
129# Flag used to choose the power state format viz Extended State-ID or the
130# Original format.
131PSCI_EXTENDED_STATE_ID := 0
132
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100133# Enable RAS support
134RAS_EXTENSION := 0
135
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100136# By default, BL1 acts as the reset handler, not BL31
137RESET_TO_BL31 := 0
138
139# For Chain of Trust
140SAVE_KEYS := 0
141
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100142# Software Delegated Exception support
143SDEI_SUPPORT := 0
144
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100145# Whether code and read-only data should be put on separate memory pages. The
146# platform Makefile is free to override this value.
147SEPARATE_CODE_AND_RODATA := 0
148
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100149# Default to SMCCC Version 1.X
150SMCCC_MAJOR_VERSION := 1
151
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100152# SPD choice
153SPD := none
154
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100155# For including the Secure Partition Manager
156ENABLE_SPM := 0
157
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100158# Flag to introduce an infinite loop in BL1 just before it exits into the next
159# image. This is meant to help debugging the post-BL2 phase.
160SPIN_ON_BL1_EXIT := 0
161
162# Flags to build TF with Trusted Boot support
163TRUSTED_BOARD_BOOT := 0
164
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100165# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100166USE_COHERENT_MEM := 1
167
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100168# Build option to choose whether Trusted Firmware uses library at ROM
169USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100170
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900171# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100172USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900173
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100174# Build verbosity
175V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100176
177# Whether to enable D-Cache early during warm boot. This is usually
178# applicable for platforms wherein interconnect programming is not
179# required to enable cache coherency after warm reset (eg: single cluster
180# platforms).
181WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100182
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100183# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100184ENABLE_SPE_FOR_LOWER_ELS := 1
185
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100186# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100187ifeq (${ARCH},aarch32)
188 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100189endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100190
191ENABLE_AMU := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100192
193# By default, enable Scalable Vector Extension if implemented for Non-secure
194# lower ELs
195# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
196ifneq (${ARCH},aarch32)
197 ENABLE_SVE_FOR_NS := 1
198else
199 override ENABLE_SVE_FOR_NS := 0
200endif