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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01008#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
10#include <bl_common.h>
11#include <context.h>
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000012#include <context_mgmt.h>
Dan Handley714a0d22014-04-09 13:13:04 +010013#include <debug.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010014#include <platform.h>
Andrew Thoelke4e126072014-06-04 21:10:52 +010015#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000016#include <utils.h>
Dan Handley714a0d22014-04-09 13:13:04 +010017#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Achin Gupta607084e2014-02-09 18:24:19 +000019/*
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000020 * SPD power management operations, expected to be supplied by the registered
21 * SPD on successful SP initialization
Achin Gupta607084e2014-02-09 18:24:19 +000022 */
Dan Handleye2712bc2014-04-10 15:37:22 +010023const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +000024
Soby Mathew981487a2015-07-13 14:10:57 +010025/*
26 * PSCI requested local power state map. This array is used to store the local
27 * power states requested by a CPU for power levels from level 1 to
28 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power
29 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
30 * CPU are the same.
31 *
32 * During state coordination, the platform is passed an array containing the
33 * local states requested for a particular non cpu power domain by each cpu
34 * within the domain.
35 *
36 * TODO: Dense packing of the requested states will cause cache thrashing
37 * when multiple power domains write to it. If we allocate the requested
38 * states at each power level in a cache-line aligned per-domain memory,
39 * the cache thrashing can be avoided.
40 */
41static plat_local_state_t
42 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
43
44
Achin Gupta4f6ad662013-10-25 09:08:21 +010045/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010046 * Arrays that hold the platform's power domain tree information for state
47 * management of power domains.
48 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
49 * which is an ancestor of a CPU power domain.
50 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010052non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
Soby Mathew2ae20432015-01-08 18:02:44 +000053#if USE_COHERENT_MEM
Soren Brinkmann46dd1702016-01-14 10:11:05 -080054__section("tzfw_coherent_mem")
Soby Mathew2ae20432015-01-08 18:02:44 +000055#endif
56;
Achin Gupta4f6ad662013-10-25 09:08:21 +010057
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +000058/* Lock for PSCI state coordination */
59DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +010060
Soby Mathew981487a2015-07-13 14:10:57 +010061cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
62
Achin Gupta4f6ad662013-10-25 09:08:21 +010063/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010064 * Pointer to functions exported by the platform to complete power mgmt. ops
65 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010066const plat_psci_ops_t *psci_plat_pm_ops;
Achin Gupta4f6ad662013-10-25 09:08:21 +010067
Soby Mathew981487a2015-07-13 14:10:57 +010068/******************************************************************************
69 * Check that the maximum power level supported by the platform makes sense
70 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010071CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
72 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
73 assert_platform_max_pwrlvl_check);
Soby Mathew2b7de2b2015-02-12 14:45:02 +000074
Soby Mathew981487a2015-07-13 14:10:57 +010075/*
76 * The plat_local_state used by the platform is one of these types: RUN,
77 * RETENTION and OFF. The platform can define further sub-states for each type
78 * apart from RUN. This categorization is done to verify the sanity of the
79 * psci_power_state passed by the platform and to print debug information. The
80 * categorization is done on the basis of the following conditions:
81 *
82 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN.
83 *
84 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is
85 * STATE_TYPE_RETN.
86 *
87 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is
88 * STATE_TYPE_OFF.
89 */
90typedef enum plat_local_state_type {
91 STATE_TYPE_RUN = 0,
92 STATE_TYPE_RETN,
93 STATE_TYPE_OFF
94} plat_local_state_type_t;
95
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010096/* Function used to categorize plat_local_state. */
97static plat_local_state_type_t find_local_state_type(plat_local_state_t state)
98{
99 if (state != 0U) {
100 if (state > PLAT_MAX_RET_STATE) {
101 return STATE_TYPE_OFF;
102 } else {
103 return STATE_TYPE_RETN;
104 }
105 } else {
106 return STATE_TYPE_RUN;
107 }
108}
Soby Mathew981487a2015-07-13 14:10:57 +0100109
110/******************************************************************************
111 * Check that the maximum retention level supported by the platform is less
112 * than the maximum off level.
113 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100114CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE,
Soby Mathew981487a2015-07-13 14:10:57 +0100115 assert_platform_max_off_and_retn_state_check);
116
117/******************************************************************************
118 * This function ensures that the power state parameter in a CPU_SUSPEND request
119 * is valid. If so, it returns the requested states for each power level.
120 *****************************************************************************/
121int psci_validate_power_state(unsigned int power_state,
122 psci_power_state_t *state_info)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100123{
Soby Mathew981487a2015-07-13 14:10:57 +0100124 /* Check SBZ bits in power state are zero */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100125 if (psci_check_power_state(power_state) != 0U)
Soby Mathew981487a2015-07-13 14:10:57 +0100126 return PSCI_E_INVALID_PARAMS;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100127
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100128 assert(psci_plat_pm_ops->validate_power_state != NULL);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100129
Soby Mathew981487a2015-07-13 14:10:57 +0100130 /* Validate the power_state using platform pm_ops */
131 return psci_plat_pm_ops->validate_power_state(power_state, state_info);
132}
Achin Guptaf6b9e992014-07-31 11:19:11 +0100133
Soby Mathew981487a2015-07-13 14:10:57 +0100134/******************************************************************************
135 * This function retrieves the `psci_power_state_t` for system suspend from
136 * the platform.
137 *****************************************************************************/
138void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
139{
140 /*
141 * Assert that the required pm_ops hook is implemented to ensure that
142 * the capability detected during psci_setup() is valid.
143 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100144 assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL);
Soby Mathew981487a2015-07-13 14:10:57 +0100145
146 /*
147 * Query the platform for the power_state required for system suspend
148 */
149 psci_plat_pm_ops->get_sys_suspend_power_state(state_info);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100150}
151
152/*******************************************************************************
Soby Mathew96168382014-12-17 14:47:57 +0000153 * This function verifies that the all the other cores in the system have been
154 * turned OFF and the current CPU is the last running CPU in the system.
155 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
156 * otherwise.
157 ******************************************************************************/
158unsigned int psci_is_last_on_cpu(void)
159{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100160 int cpu_idx, my_idx = (int) plat_my_core_pos();
Soby Mathew96168382014-12-17 14:47:57 +0000161
Soby Mathew981487a2015-07-13 14:10:57 +0100162 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
163 if (cpu_idx == my_idx) {
164 assert(psci_get_aff_info_state() == AFF_STATE_ON);
Soby Mathew96168382014-12-17 14:47:57 +0000165 continue;
166 }
167
Soby Mathew981487a2015-07-13 14:10:57 +0100168 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
Soby Mathew96168382014-12-17 14:47:57 +0000169 return 0;
170 }
171
172 return 1;
173}
174
175/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100176 * Routine to return the maximum power level to traverse to after a cpu has
177 * been physically powered up. It is expected to be called immediately after
178 * reset from assembler code.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100179 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100180static unsigned int get_power_on_target_pwrlvl(void)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100181{
Soby Mathew011ca182015-07-29 17:05:03 +0100182 unsigned int pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100183
184 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100185 * Assume that this cpu was suspended and retrieve its target power
186 * level. If it is invalid then it could only have been turned off
187 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a
188 * cpu can be turned off to.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100189 */
Soby Mathew981487a2015-07-13 14:10:57 +0100190 pwrlvl = psci_get_suspend_pwrlvl();
Soby Mathew011ca182015-07-29 17:05:03 +0100191 if (pwrlvl == PSCI_INVALID_PWR_LVL)
Soby Mathew981487a2015-07-13 14:10:57 +0100192 pwrlvl = PLAT_MAX_PWR_LVL;
193 return pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100194}
195
Soby Mathew981487a2015-07-13 14:10:57 +0100196/******************************************************************************
197 * Helper function to update the requested local power state array. This array
198 * does not store the requested state for the CPU power level. Hence an
199 * assertion is added to prevent us from accessing the wrong index.
200 *****************************************************************************/
201static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
202 unsigned int cpu_idx,
203 plat_local_state_t req_pwr_state)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100204{
Alistair Francis16484dd2017-08-23 13:55:21 -0700205 /*
206 * This should never happen, we have this here to avoid
207 * "array subscript is above array bounds" errors in GCC.
208 */
Soby Mathew981487a2015-07-13 14:10:57 +0100209 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Alistair Francis16484dd2017-08-23 13:55:21 -0700210#pragma GCC diagnostic push
211#pragma GCC diagnostic ignored "-Warray-bounds"
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100212 psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
Alistair Francis16484dd2017-08-23 13:55:21 -0700213#pragma GCC diagnostic pop
Achin Guptaf6b9e992014-07-31 11:19:11 +0100214}
215
Soby Mathew981487a2015-07-13 14:10:57 +0100216/******************************************************************************
217 * This function initializes the psci_req_local_pwr_states.
218 *****************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +0100219void __init psci_init_req_local_pwr_states(void)
Achin Guptaa45e3972013-12-05 15:10:48 +0000220{
Soby Mathew981487a2015-07-13 14:10:57 +0100221 /* Initialize the requested state of all non CPU power domains as OFF */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100222 unsigned int pwrlvl;
223 int core;
224
225 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
226 for (core = 0; core < PLATFORM_CORE_COUNT; core++) {
227 psci_req_local_pwr_states[pwrlvl][core] =
228 PLAT_MAX_OFF_STATE;
229 }
230 }
Soby Mathew981487a2015-07-13 14:10:57 +0100231}
Achin Guptaa45e3972013-12-05 15:10:48 +0000232
Soby Mathew981487a2015-07-13 14:10:57 +0100233/******************************************************************************
234 * Helper function to return a reference to an array containing the local power
235 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the
236 * array will be the number of cpu power domains of which this power domain is
237 * an ancestor. These requested states will be used to determine a suitable
238 * target state for this power domain during psci state coordination. An
239 * assertion is added to prevent us from accessing the CPU power level.
240 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100241static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100242 int cpu_idx)
Soby Mathew981487a2015-07-13 14:10:57 +0100243{
244 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100245
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100246 return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
Soby Mathew981487a2015-07-13 14:10:57 +0100247}
Achin Guptaa45e3972013-12-05 15:10:48 +0000248
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000249/*
250 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent
251 * memory.
252 *
253 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory,
254 * it's accessed by both cached and non-cached participants. To serve the common
255 * minimum, perform a cache flush before read and after write so that non-cached
256 * participants operate on latest data in main memory.
257 *
258 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent
259 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent.
260 * In both cases, no cache operations are required.
261 */
262
263/*
264 * Retrieve local state of non-CPU power domain node from a non-cached CPU,
265 * after any required cache maintenance operation.
266 */
267static plat_local_state_t get_non_cpu_pd_node_local_state(
268 unsigned int parent_idx)
269{
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500270#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000271 flush_dcache_range(
272 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
273 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
274#endif
275 return psci_non_cpu_pd_nodes[parent_idx].local_state;
276}
277
278/*
279 * Update local state of non-CPU power domain node from a cached CPU; perform
280 * any required cache maintenance operation afterwards.
281 */
282static void set_non_cpu_pd_node_local_state(unsigned int parent_idx,
283 plat_local_state_t state)
284{
285 psci_non_cpu_pd_nodes[parent_idx].local_state = state;
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500286#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000287 flush_dcache_range(
288 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
289 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
290#endif
291}
292
Soby Mathew981487a2015-07-13 14:10:57 +0100293/******************************************************************************
294 * Helper function to return the current local power state of each power domain
295 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This
296 * function will be called after a cpu is powered on to find the local state
297 * each power domain has emerged from.
298 *****************************************************************************/
Achin Gupta9b2bf252016-06-28 16:46:15 +0100299void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
300 psci_power_state_t *target_state)
Soby Mathew981487a2015-07-13 14:10:57 +0100301{
Soby Mathew011ca182015-07-29 17:05:03 +0100302 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100303 plat_local_state_t *pd_state = target_state->pwr_domain_state;
304
305 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state();
306 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
307
308 /* Copy the local power state from node to state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100309 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000310 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx);
Soby Mathew981487a2015-07-13 14:10:57 +0100311 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
312 }
313
314 /* Set the the higher levels to RUN */
315 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
316 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
317}
318
319/******************************************************************************
320 * Helper function to set the target local power state that each power domain
321 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will
322 * enter. This function will be called after coordination of requested power
323 * states has been done for each power level.
324 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100325static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100326 const psci_power_state_t *target_state)
327{
Soby Mathew011ca182015-07-29 17:05:03 +0100328 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100329 const plat_local_state_t *pd_state = target_state->pwr_domain_state;
330
331 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]);
Achin Guptaa45e3972013-12-05 15:10:48 +0000332
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100333 /*
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000334 * Need to flush as local_state might be accessed with Data Cache
Soby Mathew981487a2015-07-13 14:10:57 +0100335 * disabled during power on
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100336 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000337 psci_flush_cpu_data(psci_svc_cpu_data.local_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100338
339 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
340
341 /* Copy the local_state from state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100342 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000343 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]);
Soby Mathew981487a2015-07-13 14:10:57 +0100344 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
345 }
Achin Guptaa45e3972013-12-05 15:10:48 +0000346}
347
Soby Mathew981487a2015-07-13 14:10:57 +0100348
Achin Guptaa45e3972013-12-05 15:10:48 +0000349/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100350 * PSCI helper function to get the parent nodes corresponding to a cpu_index.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351 ******************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100352void psci_get_parent_pwr_domain_nodes(int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100353 unsigned int end_lvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100354 unsigned int *node_index)
Soby Mathew981487a2015-07-13 14:10:57 +0100355{
356 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
Varun Wadekar66231d12017-06-07 09:57:42 -0700357 unsigned int i;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100358 unsigned int *node = node_index;
Soby Mathew981487a2015-07-13 14:10:57 +0100359
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100360 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) {
361 *node = parent_node;
362 node++;
Soby Mathew981487a2015-07-13 14:10:57 +0100363 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
364 }
365}
366
367/******************************************************************************
368 * This function is invoked post CPU power up and initialization. It sets the
369 * affinity info state, target power state and requested power state for the
370 * current CPU and all its ancestor power domains to RUN.
371 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100372void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl)
Soby Mathew981487a2015-07-13 14:10:57 +0100373{
Soby Mathew011ca182015-07-29 17:05:03 +0100374 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100375 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
376
377 /* Reset the local_state to RUN for the non cpu power domains. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100378 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000379 set_non_cpu_pd_node_local_state(parent_idx,
380 PSCI_LOCAL_STATE_RUN);
Soby Mathew981487a2015-07-13 14:10:57 +0100381 psci_set_req_local_pwr_state(lvl,
382 cpu_idx,
383 PSCI_LOCAL_STATE_RUN);
384 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
385 }
386
387 /* Set the affinity info state to ON */
388 psci_set_aff_info_state(AFF_STATE_ON);
389
390 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000391 psci_flush_cpu_data(psci_svc_cpu_data);
Soby Mathew981487a2015-07-13 14:10:57 +0100392}
393
394/******************************************************************************
395 * This function is passed the local power states requested for each power
396 * domain (state_info) between the current CPU domain and its ancestors until
397 * the target power level (end_pwrlvl). It updates the array of requested power
398 * states with this information.
399 *
400 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
401 * retrieves the states requested by all the cpus of which the power domain at
402 * that level is an ancestor. It passes this information to the platform to
403 * coordinate and return the target power state. If the target state for a level
404 * is RUN then subsequent levels are not considered. At the CPU level, state
405 * coordination is not required. Hence, the requested and the target states are
406 * the same.
407 *
408 * The 'state_info' is updated with the target state for each level between the
409 * CPU and the 'end_pwrlvl' and returned to the caller.
410 *
411 * This function will only be invoked with data cache enabled and while
412 * powering down a core.
413 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100414void psci_do_state_coordination(unsigned int end_pwrlvl,
415 psci_power_state_t *state_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100416{
Soby Mathew981487a2015-07-13 14:10:57 +0100417 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100418 int start_idx;
419 unsigned int ncpus;
Soby Mathew981487a2015-07-13 14:10:57 +0100420 plat_local_state_t target_state, *req_states;
421
Soby Mathew1298e692016-02-02 14:23:10 +0000422 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100423 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
424
425 /* For level 0, the requested state will be equivalent
426 to target state */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100427 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100428
429 /* First update the requested power state */
430 psci_set_req_local_pwr_state(lvl, cpu_idx,
431 state_info->pwr_domain_state[lvl]);
432
433 /* Get the requested power states for this power level */
434 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
435 req_states = psci_get_req_local_pwr_states(lvl, start_idx);
436
437 /*
438 * Let the platform coordinate amongst the requested states at
439 * this power level and return the target local power state.
440 */
441 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus;
442 target_state = plat_get_target_pwr_state(lvl,
443 req_states,
444 ncpus);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100445
Soby Mathew981487a2015-07-13 14:10:57 +0100446 state_info->pwr_domain_state[lvl] = target_state;
447
448 /* Break early if the negotiated target power state is RUN */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100449 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
Soby Mathew981487a2015-07-13 14:10:57 +0100450 break;
451
452 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
453 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100454
455 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100456 * This is for cases when we break out of the above loop early because
457 * the target power state is RUN at a power level < end_pwlvl.
458 * We update the requested power state from state_info and then
459 * set the target state as RUN.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100460 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100461 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100462 psci_set_req_local_pwr_state(lvl, cpu_idx,
463 state_info->pwr_domain_state[lvl]);
464 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100465
Soby Mathew981487a2015-07-13 14:10:57 +0100466 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100467
Soby Mathew981487a2015-07-13 14:10:57 +0100468 /* Update the target state in the power domain nodes */
469 psci_set_target_local_pwr_states(end_pwrlvl, state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100470}
471
Soby Mathew981487a2015-07-13 14:10:57 +0100472/******************************************************************************
473 * This function validates a suspend request by making sure that if a standby
474 * state is requested then no power level is turned off and the highest power
475 * level is placed in a standby/retention state.
476 *
477 * It also ensures that the state level X will enter is not shallower than the
478 * state level X + 1 will enter.
479 *
480 * This validation will be enabled only for DEBUG builds as the platform is
481 * expected to perform these validations as well.
482 *****************************************************************************/
483int psci_validate_suspend_req(const psci_power_state_t *state_info,
484 unsigned int is_power_down_state)
Achin Gupta0959db52013-12-02 17:33:04 +0000485{
Soby Mathew981487a2015-07-13 14:10:57 +0100486 unsigned int max_off_lvl, target_lvl, max_retn_lvl;
487 plat_local_state_t state;
488 plat_local_state_type_t req_state_type, deepest_state_type;
489 int i;
Achin Gupta0959db52013-12-02 17:33:04 +0000490
Soby Mathew981487a2015-07-13 14:10:57 +0100491 /* Find the target suspend power level */
492 target_lvl = psci_find_target_suspend_lvl(state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100493 if (target_lvl == PSCI_INVALID_PWR_LVL)
Achin Gupta0959db52013-12-02 17:33:04 +0000494 return PSCI_E_INVALID_PARAMS;
495
Soby Mathew981487a2015-07-13 14:10:57 +0100496 /* All power domain levels are in a RUN state to begin with */
497 deepest_state_type = STATE_TYPE_RUN;
498
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100499 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) {
Soby Mathew981487a2015-07-13 14:10:57 +0100500 state = state_info->pwr_domain_state[i];
501 req_state_type = find_local_state_type(state);
502
503 /*
504 * While traversing from the highest power level to the lowest,
505 * the state requested for lower levels has to be the same or
506 * deeper i.e. equal to or greater than the state at the higher
507 * levels. If this condition is true, then the requested state
508 * becomes the deepest state encountered so far.
509 */
510 if (req_state_type < deepest_state_type)
511 return PSCI_E_INVALID_PARAMS;
512 deepest_state_type = req_state_type;
513 }
514
515 /* Find the highest off power level */
516 max_off_lvl = psci_find_max_off_lvl(state_info);
517
518 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */
Soby Mathew011ca182015-07-29 17:05:03 +0100519 max_retn_lvl = PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100520 if (target_lvl != max_off_lvl)
521 max_retn_lvl = target_lvl;
522
523 /*
524 * If this is not a request for a power down state then max off level
525 * has to be invalid and max retention level has to be a valid power
526 * level.
527 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100528 if ((is_power_down_state == 0U) &&
529 ((max_off_lvl != PSCI_INVALID_PWR_LVL) ||
530 (max_retn_lvl == PSCI_INVALID_PWR_LVL)))
Achin Gupta0959db52013-12-02 17:33:04 +0000531 return PSCI_E_INVALID_PARAMS;
532
533 return PSCI_E_SUCCESS;
534}
535
Soby Mathew981487a2015-07-13 14:10:57 +0100536/******************************************************************************
537 * This function finds the highest power level which will be powered down
538 * amongst all the power levels specified in the 'state_info' structure
539 *****************************************************************************/
540unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
Achin Guptacab78e42014-07-28 00:09:01 +0100541{
Soby Mathew981487a2015-07-13 14:10:57 +0100542 int i;
Achin Guptacab78e42014-07-28 00:09:01 +0100543
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100544 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
545 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0)
546 return (unsigned int) i;
Soby Mathew981487a2015-07-13 14:10:57 +0100547 }
548
Soby Mathew011ca182015-07-29 17:05:03 +0100549 return PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100550}
551
552/******************************************************************************
553 * This functions finds the level of the highest power domain which will be
554 * placed in a low power state during a suspend operation.
555 *****************************************************************************/
556unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info)
557{
558 int i;
559
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100560 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
561 if (is_local_state_run(state_info->pwr_domain_state[i]) == 0)
562 return (unsigned int) i;
Achin Guptacab78e42014-07-28 00:09:01 +0100563 }
Soby Mathew981487a2015-07-13 14:10:57 +0100564
Soby Mathew011ca182015-07-29 17:05:03 +0100565 return PSCI_INVALID_PWR_LVL;
Achin Guptacab78e42014-07-28 00:09:01 +0100566}
567
568/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100569 * This function is passed a cpu_index and the highest level in the topology
570 * tree that the operation should be applied to. It picks up locks in order of
571 * increasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000572 ******************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100573void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx)
Achin Gupta0959db52013-12-02 17:33:04 +0000574{
Soby Mathew981487a2015-07-13 14:10:57 +0100575 unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
Soby Mathew011ca182015-07-29 17:05:03 +0100576 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000577
Soby Mathew981487a2015-07-13 14:10:57 +0100578 /* No locking required for level 0. Hence start locking from level 1 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100579 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100580 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
581 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
Achin Gupta0959db52013-12-02 17:33:04 +0000582 }
583}
584
585/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100586 * This function is passed a cpu_index and the highest level in the topology
587 * tree that the operation should be applied to. It releases the locks in order
588 * of decreasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000589 ******************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100590void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx)
Achin Gupta0959db52013-12-02 17:33:04 +0000591{
Soby Mathew981487a2015-07-13 14:10:57 +0100592 unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0};
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100593 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000594
Soby Mathew981487a2015-07-13 14:10:57 +0100595 /* Get the parent nodes */
596 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
Soby Mathew523d6332015-01-08 18:02:19 +0000597
Soby Mathew981487a2015-07-13 14:10:57 +0100598 /* Unlock top down. No unlocking required for level 0. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100599 for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) {
600 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100601 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000602 }
603}
604
605/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100606 * Simple routine to determine whether a mpidr is valid or not.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100607 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100608int psci_validate_mpidr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100609{
Soby Mathew981487a2015-07-13 14:10:57 +0100610 if (plat_core_pos_by_mpidr(mpidr) < 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100611 return PSCI_E_INVALID_PARAMS;
Soby Mathew981487a2015-07-13 14:10:57 +0100612
613 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100614}
615
616/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100617 * This function determines the full entrypoint information for the requested
Soby Mathew8595b872015-01-06 15:36:38 +0000618 * PSCI entrypoint on power on/resume and returns it.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100619 ******************************************************************************/
Soby Mathew89d90dc2016-05-05 14:11:23 +0100620#ifdef AARCH32
Soby Mathewf1f97a12015-07-15 12:13:26 +0100621static int psci_get_ns_ep_info(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100622 uintptr_t entrypoint,
623 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100624{
Soby Mathew89d90dc2016-05-05 14:11:23 +0100625 u_register_t ep_attr;
626 unsigned int aif, ee, mode;
627 u_register_t scr = read_scr();
628 u_register_t ns_sctlr, sctlr;
629
630 /* Switch to non secure state */
631 write_scr(scr | SCR_NS_BIT);
632 isb();
633 ns_sctlr = read_sctlr();
634
635 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
636
637 /* Return to original state */
638 write_scr(scr);
639 isb();
640 ee = 0;
641
642 ep_attr = NON_SECURE | EP_ST_DISABLE;
643 if (sctlr & SCTLR_EE_BIT) {
644 ep_attr |= EP_EE_BIG;
645 ee = 1;
646 }
647 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
648
649 ep->pc = entrypoint;
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000650 zeromem(&ep->args, sizeof(ep->args));
Soby Mathew89d90dc2016-05-05 14:11:23 +0100651 ep->args.arg0 = context_id;
652
653 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
654
655 /*
656 * TODO: Choose async. exception bits if HYP mode is not
657 * implemented according to the values of SCR.{AW, FW} bits
658 */
659 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
660
661 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
662
663 return PSCI_E_SUCCESS;
664}
665
666#else
667static int psci_get_ns_ep_info(entry_point_info_t *ep,
668 uintptr_t entrypoint,
669 u_register_t context_id)
670{
Soby Mathewa0fedc42016-06-16 14:52:04 +0100671 u_register_t ep_attr, sctlr;
Soby Mathew011ca182015-07-29 17:05:03 +0100672 unsigned int daif, ee, mode;
Soby Mathewa0fedc42016-06-16 14:52:04 +0100673 u_register_t ns_scr_el3 = read_scr_el3();
674 u_register_t ns_sctlr_el1 = read_sctlr_el1();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100675
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100676 sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
677 read_sctlr_el2() : ns_sctlr_el1;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100678 ee = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100679
Andrew Thoelke4e126072014-06-04 21:10:52 +0100680 ep_attr = NON_SECURE | EP_ST_DISABLE;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100681 if ((sctlr & SCTLR_EE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100682 ep_attr |= EP_EE_BIG;
683 ee = 1;
684 }
Soby Mathew8595b872015-01-06 15:36:38 +0000685 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100686
Soby Mathew8595b872015-01-06 15:36:38 +0000687 ep->pc = entrypoint;
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000688 zeromem(&ep->args, sizeof(ep->args));
Soby Mathew8595b872015-01-06 15:36:38 +0000689 ep->args.arg0 = context_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100690
691 /*
692 * Figure out whether the cpu enters the non-secure address space
693 * in aarch32 or aarch64
694 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100695 if ((ns_scr_el3 & SCR_RW_BIT) != 0U) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100696
697 /*
698 * Check whether a Thumb entry point has been provided for an
699 * aarch64 EL
700 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100701 if ((entrypoint & 0x1UL) != 0UL)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100702 return PSCI_E_INVALID_ADDRESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100703
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100704 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100705
Soby Mathew8595b872015-01-06 15:36:38 +0000706 ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100707 } else {
708
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100709 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
710 MODE32_hyp : MODE32_svc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100711
712 /*
713 * TODO: Choose async. exception bits if HYP mode is not
714 * implemented according to the values of SCR.{AW, FW} bits
715 */
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100716 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
717
Soby Mathew8595b872015-01-06 15:36:38 +0000718 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100719 }
720
Andrew Thoelke4e126072014-06-04 21:10:52 +0100721 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100722}
Soby Mathew89d90dc2016-05-05 14:11:23 +0100723#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100724
725/*******************************************************************************
Soby Mathewf1f97a12015-07-15 12:13:26 +0100726 * This function validates the entrypoint with the platform layer if the
727 * appropriate pm_ops hook is exported by the platform and returns the
728 * 'entry_point_info'.
729 ******************************************************************************/
730int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100731 uintptr_t entrypoint,
732 u_register_t context_id)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100733{
734 int rc;
735
736 /* Validate the entrypoint using platform psci_ops */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100737 if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100738 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
739 if (rc != PSCI_E_SUCCESS)
740 return PSCI_E_INVALID_ADDRESS;
741 }
742
743 /*
744 * Verify and derive the re-entry information for
745 * the non-secure world from the non-secure state from
746 * where this call originated.
747 */
748 rc = psci_get_ns_ep_info(ep, entrypoint, context_id);
749 return rc;
750}
751
752/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100753 * Generic handler which is called when a cpu is physically powered on. It
Soby Mathew981487a2015-07-13 14:10:57 +0100754 * traverses the node information and finds the highest power level powered
755 * off and performs generic, architectural, platform setup and state management
756 * to power on that power level and power levels below it.
757 * e.g. For a cpu that's been powered on, it will call the platform specific
758 * code to enable the gic cpu interface and for a cluster it will enable
759 * coherency at the interconnect level in addition to gic cpu interface.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100760 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100761void psci_warmboot_entrypoint(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100762{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100763 unsigned int end_pwrlvl;
764 int cpu_idx = (int) plat_my_core_pos();
Soby Mathew981487a2015-07-13 14:10:57 +0100765 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100766
Achin Gupta4f6ad662013-10-25 09:08:21 +0100767 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100768 * Verify that we have been explicitly turned ON or resumed from
769 * suspend.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100770 */
Soby Mathew981487a2015-07-13 14:10:57 +0100771 if (psci_get_aff_info_state() == AFF_STATE_OFF) {
772 ERROR("Unexpected affinity info state");
James Morrissey40a6f642014-02-10 14:24:36 +0000773 panic();
Soby Mathew981487a2015-07-13 14:10:57 +0100774 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100775
776 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100777 * Get the maximum power domain level to traverse to after this cpu
778 * has been physically powered up.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100779 */
Soby Mathew981487a2015-07-13 14:10:57 +0100780 end_pwrlvl = get_power_on_target_pwrlvl();
Achin Guptaf6b9e992014-07-31 11:19:11 +0100781
782 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100783 * This function acquires the lock corresponding to each power level so
784 * that by the time all locks are taken, the system topology is snapshot
785 * and state management can be done safely.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100786 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100787 psci_acquire_pwr_domain_locks(end_pwrlvl, cpu_idx);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100788
Soby Mathew8336f682017-10-16 15:19:31 +0100789 psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
790
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100791#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000792 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100793#endif
794
Achin Gupta4f6ad662013-10-25 09:08:21 +0100795 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100796 * This CPU could be resuming from suspend or it could have just been
797 * turned on. To distinguish between these 2 cases, we examine the
798 * affinity state of the CPU:
799 * - If the affinity state is ON_PENDING then it has just been
800 * turned on.
801 * - Else it is resuming from suspend.
802 *
803 * Depending on the type of warm reset identified, choose the right set
804 * of power management handler and perform the generic, architecture
805 * and platform specific handling.
Achin Guptacab78e42014-07-28 00:09:01 +0100806 */
Soby Mathew981487a2015-07-13 14:10:57 +0100807 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
808 psci_cpu_on_finish(cpu_idx, &state_info);
809 else
810 psci_cpu_suspend_finish(cpu_idx, &state_info);
Achin Guptacab78e42014-07-28 00:09:01 +0100811
812 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100813 * Set the requested and target state of this CPU and all the higher
814 * power domains which are ancestors of this CPU to run.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100815 */
Soby Mathew981487a2015-07-13 14:10:57 +0100816 psci_set_pwr_domains_to_run(end_pwrlvl);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100817
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100818#if ENABLE_PSCI_STAT
819 /*
820 * Update PSCI stats.
821 * Caches are off when writing stats data on the power down path.
822 * Since caches are now enabled, it's necessary to do cache
823 * maintenance before reading that same data.
824 */
dp-arm66abfbe2017-01-31 13:01:04 +0000825 psci_stats_update_pwr_up(end_pwrlvl, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100826#endif
827
Achin Guptaf6b9e992014-07-31 11:19:11 +0100828 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100829 * This loop releases the lock corresponding to each power level
Achin Gupta0959db52013-12-02 17:33:04 +0000830 * in the reverse order to which they were acquired.
831 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100832 psci_release_pwr_domain_locks(end_pwrlvl, cpu_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100833}
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000834
835/*******************************************************************************
836 * This function initializes the set of hooks that PSCI invokes as part of power
837 * management operation. The power management hooks are expected to be provided
838 * by the SPD, after it finishes all its initialization
839 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100840void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000841{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100842 assert(pm != NULL);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000843 psci_spd_pm = pm;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000844
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100845 if (pm->svc_migrate != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000846 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
847
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100848 if (pm->svc_migrate_info != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000849 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
850 | define_psci_cap(PSCI_MIG_INFO_TYPE);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000851}
Juan Castillo4dc4a472014-08-12 11:17:06 +0100852
853/*******************************************************************************
Soby Mathew110fe362014-10-23 10:35:34 +0100854 * This function invokes the migrate info hook in the spd_pm_ops. It performs
855 * the necessary return value validation. If the Secure Payload is UP and
856 * migrate capable, it returns the mpidr of the CPU on which the Secure payload
857 * is resident through the mpidr parameter. Else the value of the parameter on
858 * return is undefined.
859 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100860int psci_spd_migrate_info(u_register_t *mpidr)
Soby Mathew110fe362014-10-23 10:35:34 +0100861{
862 int rc;
863
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100864 if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL))
Soby Mathew110fe362014-10-23 10:35:34 +0100865 return PSCI_E_NOT_SUPPORTED;
866
867 rc = psci_spd_pm->svc_migrate_info(mpidr);
868
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100869 assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) ||
870 (rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED));
Soby Mathew110fe362014-10-23 10:35:34 +0100871
872 return rc;
873}
874
875
876/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100877 * This function prints the state of all power domains present in the
Juan Castillo4dc4a472014-08-12 11:17:06 +0100878 * system
879 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100880void psci_print_power_domain_map(void)
Juan Castillo4dc4a472014-08-12 11:17:06 +0100881{
882#if LOG_LEVEL >= LOG_LEVEL_INFO
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100883 int idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100884 plat_local_state_t state;
885 plat_local_state_type_t state_type;
886
Juan Castillo4dc4a472014-08-12 11:17:06 +0100887 /* This array maps to the PSCI_STATE_X definitions in psci.h */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100888 static const char * const psci_state_type_str[] = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100889 "ON",
Soby Mathew981487a2015-07-13 14:10:57 +0100890 "RETENTION",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100891 "OFF",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100892 };
893
Soby Mathew981487a2015-07-13 14:10:57 +0100894 INFO("PSCI Power Domain Map:\n");
895 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT);
896 idx++) {
897 state_type = find_local_state_type(
898 psci_non_cpu_pd_nodes[idx].local_state);
899 INFO(" Domain Node : Level %u, parent_node %d,"
900 " State %s (0x%x)\n",
901 psci_non_cpu_pd_nodes[idx].level,
902 psci_non_cpu_pd_nodes[idx].parent_node,
903 psci_state_type_str[state_type],
904 psci_non_cpu_pd_nodes[idx].local_state);
905 }
906
907 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) {
908 state = psci_get_cpu_local_state_by_idx(idx);
909 state_type = find_local_state_type(state);
Soby Mathewa0fedc42016-06-16 14:52:04 +0100910 INFO(" CPU Node : MPID 0x%llx, parent_node %d,"
Soby Mathew981487a2015-07-13 14:10:57 +0100911 " State %s (0x%x)\n",
Soby Mathewa0fedc42016-06-16 14:52:04 +0100912 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr,
Soby Mathew981487a2015-07-13 14:10:57 +0100913 psci_cpu_pd_nodes[idx].parent_node,
914 psci_state_type_str[state_type],
915 psci_get_cpu_local_state_by_idx(idx));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100916 }
917#endif
918}
Soby Mathew981487a2015-07-13 14:10:57 +0100919
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000920/******************************************************************************
921 * Return whether any secondaries were powered up with CPU_ON call. A CPU that
922 * have ever been powered up would have set its MPDIR value to something other
923 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to
924 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is
925 * meaningful only when called on the primary CPU during early boot.
926 *****************************************************************************/
927int psci_secondaries_brought_up(void)
928{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100929 unsigned int idx, n_valid = 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000930
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100931 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) {
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000932 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR)
933 n_valid++;
934 }
935
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100936 assert(n_valid > 0U);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000937
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100938 return (n_valid > 1U) ? 1 : 0;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000939}
940
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000941/*******************************************************************************
942 * Initiate power down sequence, by calling power down operations registered for
943 * this CPU.
944 ******************************************************************************/
945void psci_do_pwrdown_sequence(unsigned int power_level)
946{
947#if HW_ASSISTED_COHERENCY
948 /*
949 * With hardware-assisted coherency, the CPU drivers only initiate the
950 * power down sequence, without performing cache-maintenance operations
Andrew F. Davis564f9542018-08-30 12:08:01 -0500951 * in software. Data caches enabled both before and after this call.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000952 */
953 prepare_cpu_pwr_dwn(power_level);
954#else
955 /*
956 * Without hardware-assisted coherency, the CPU drivers disable data
Andrew F. Davis564f9542018-08-30 12:08:01 -0500957 * caches, then perform cache-maintenance operations in software.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000958 *
Andrew F. Davis564f9542018-08-30 12:08:01 -0500959 * This also calls prepare_cpu_pwr_dwn() to initiate power down
960 * sequence, but that function will return with data caches disabled.
961 * We must ensure that the stack memory is flushed out to memory before
962 * we start popping from it again.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000963 */
964 psci_do_pwrdown_cache_maintenance(power_level);
965#endif
966}