Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 1 | /* |
David Cunado | 28f69ab | 2017-04-05 11:34:03 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #ifndef __TSPD_PRIVATE_H__ |
| 32 | #define __TSPD_PRIVATE_H__ |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 33 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 34 | #include <arch.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 35 | #include <context.h> |
Achin Gupta | aeaab68 | 2014-05-09 13:21:31 +0100 | [diff] [blame] | 36 | #include <interrupt_mgmt.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | #include <platform_def.h> |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 38 | #include <psci.h> |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
| 41 | * Secure Payload PM state information e.g. SP is suspended, uninitialised etc |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 42 | * and macros to access the state information in the per-cpu 'state' flags |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 43 | ******************************************************************************/ |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 44 | #define TSP_PSTATE_OFF 0 |
| 45 | #define TSP_PSTATE_ON 1 |
| 46 | #define TSP_PSTATE_SUSPEND 2 |
| 47 | #define TSP_PSTATE_SHIFT 0 |
| 48 | #define TSP_PSTATE_MASK 0x3 |
| 49 | #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) |
| 50 | #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ |
| 51 | << TSP_PSTATE_SHIFT)) |
| 52 | #define set_tsp_pstate(st, pst) do { \ |
| 53 | clr_tsp_pstate(st); \ |
| 54 | st |= (pst & TSP_PSTATE_MASK) << \ |
| 55 | TSP_PSTATE_SHIFT; \ |
| 56 | } while (0); |
| 57 | |
| 58 | |
| 59 | /* |
David Cunado | 28f69ab | 2017-04-05 11:34:03 +0100 | [diff] [blame^] | 60 | * This flag is used by the TSPD to determine if the TSP is servicing a yielding |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 61 | * SMC request prior to programming the next entry into the TSP e.g. if TSP |
| 62 | * execution is preempted by a non-secure interrupt and handed control to the |
| 63 | * normal world. If another request which is distinct from what the TSP was |
| 64 | * previously doing arrives, then this flag will be help the TSPD to either |
| 65 | * reject the new request or service it while ensuring that the previous context |
| 66 | * is not corrupted. |
| 67 | */ |
David Cunado | 28f69ab | 2017-04-05 11:34:03 +0100 | [diff] [blame^] | 68 | #define YIELD_SMC_ACTIVE_FLAG_SHIFT 2 |
| 69 | #define YIELD_SMC_ACTIVE_FLAG_MASK 1 |
| 70 | #define get_yield_smc_active_flag(state) \ |
| 71 | ((state >> YIELD_SMC_ACTIVE_FLAG_SHIFT) \ |
| 72 | & YIELD_SMC_ACTIVE_FLAG_MASK) |
| 73 | #define set_yield_smc_active_flag(state) (state |= \ |
| 74 | 1 << YIELD_SMC_ACTIVE_FLAG_SHIFT) |
| 75 | #define clr_yield_smc_active_flag(state) (state &= \ |
| 76 | ~(YIELD_SMC_ACTIVE_FLAG_MASK \ |
| 77 | << YIELD_SMC_ACTIVE_FLAG_SHIFT)) |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 78 | |
| 79 | /******************************************************************************* |
| 80 | * Secure Payload execution state information i.e. aarch32 or aarch64 |
| 81 | ******************************************************************************/ |
| 82 | #define TSP_AARCH32 MODE_RW_32 |
| 83 | #define TSP_AARCH64 MODE_RW_64 |
| 84 | |
| 85 | /******************************************************************************* |
| 86 | * The SPD should know the type of Secure Payload. |
| 87 | ******************************************************************************/ |
| 88 | #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP |
| 89 | #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP |
| 90 | #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP |
| 91 | |
| 92 | /******************************************************************************* |
| 93 | * Secure Payload migrate type information as known to the SPD. We assume that |
| 94 | * the SPD is dealing with an MP Secure Payload. |
| 95 | ******************************************************************************/ |
| 96 | #define TSP_MIGRATE_INFO TSP_TYPE_MP |
| 97 | |
| 98 | /******************************************************************************* |
| 99 | * Number of cpus that the present on this platform. TODO: Rely on a topology |
| 100 | * tree to determine this in the future to avoid assumptions about mpidr |
| 101 | * allocation |
| 102 | ******************************************************************************/ |
| 103 | #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT |
| 104 | |
| 105 | /******************************************************************************* |
| 106 | * Constants that allow assembler code to preserve callee-saved registers of the |
| 107 | * C runtime context while performing a security state switch. |
| 108 | ******************************************************************************/ |
| 109 | #define TSPD_C_RT_CTX_X19 0x0 |
| 110 | #define TSPD_C_RT_CTX_X20 0x8 |
| 111 | #define TSPD_C_RT_CTX_X21 0x10 |
| 112 | #define TSPD_C_RT_CTX_X22 0x18 |
| 113 | #define TSPD_C_RT_CTX_X23 0x20 |
| 114 | #define TSPD_C_RT_CTX_X24 0x28 |
| 115 | #define TSPD_C_RT_CTX_X25 0x30 |
| 116 | #define TSPD_C_RT_CTX_X26 0x38 |
| 117 | #define TSPD_C_RT_CTX_X27 0x40 |
| 118 | #define TSPD_C_RT_CTX_X28 0x48 |
| 119 | #define TSPD_C_RT_CTX_X29 0x50 |
| 120 | #define TSPD_C_RT_CTX_X30 0x58 |
| 121 | #define TSPD_C_RT_CTX_SIZE 0x60 |
| 122 | #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) |
| 123 | |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 124 | /******************************************************************************* |
| 125 | * Constants that allow assembler code to preserve caller-saved registers of the |
| 126 | * SP context while performing a TSP preemption. |
| 127 | * Note: These offsets have to match with the offsets for the corresponding |
| 128 | * registers in cpu_context as we are using memcpy to copy the values from |
| 129 | * cpu_context to sp_ctx. |
| 130 | ******************************************************************************/ |
| 131 | #define TSPD_SP_CTX_X0 0x0 |
| 132 | #define TSPD_SP_CTX_X1 0x8 |
| 133 | #define TSPD_SP_CTX_X2 0x10 |
| 134 | #define TSPD_SP_CTX_X3 0x18 |
| 135 | #define TSPD_SP_CTX_X4 0x20 |
| 136 | #define TSPD_SP_CTX_X5 0x28 |
| 137 | #define TSPD_SP_CTX_X6 0x30 |
| 138 | #define TSPD_SP_CTX_X7 0x38 |
| 139 | #define TSPD_SP_CTX_X8 0x40 |
| 140 | #define TSPD_SP_CTX_X9 0x48 |
| 141 | #define TSPD_SP_CTX_X10 0x50 |
| 142 | #define TSPD_SP_CTX_X11 0x58 |
| 143 | #define TSPD_SP_CTX_X12 0x60 |
| 144 | #define TSPD_SP_CTX_X13 0x68 |
| 145 | #define TSPD_SP_CTX_X14 0x70 |
| 146 | #define TSPD_SP_CTX_X15 0x78 |
| 147 | #define TSPD_SP_CTX_X16 0x80 |
| 148 | #define TSPD_SP_CTX_X17 0x88 |
| 149 | #define TSPD_SP_CTX_SIZE 0x90 |
| 150 | #define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) |
| 151 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 152 | #ifndef __ASSEMBLY__ |
| 153 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 154 | #include <cassert.h> |
| 155 | #include <stdint.h> |
| 156 | |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 157 | /* |
| 158 | * The number of arguments to save during a SMC call for TSP. |
| 159 | * Currently only x1 and x2 are used by TSP. |
| 160 | */ |
| 161 | #define TSP_NUM_ARGS 0x2 |
| 162 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 163 | /* AArch64 callee saved general purpose register context structure. */ |
| 164 | DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); |
| 165 | |
| 166 | /* |
| 167 | * Compile time assertion to ensure that both the compiler and linker |
| 168 | * have the same double word aligned view of the size of the C runtime |
| 169 | * register context. |
| 170 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 171 | CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 172 | assert_spd_c_rt_regs_size_mismatch); |
| 173 | |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 174 | /* SEL1 Secure payload (SP) caller saved register context structure. */ |
| 175 | DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES); |
| 176 | |
| 177 | /* |
| 178 | * Compile time assertion to ensure that both the compiler and linker |
| 179 | * have the same double word aligned view of the size of the C runtime |
| 180 | * register context. |
| 181 | */ |
| 182 | CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \ |
| 183 | assert_spd_sp_regs_size_mismatch); |
| 184 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 185 | /******************************************************************************* |
| 186 | * Structure which helps the SPD to maintain the per-cpu state of the SP. |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 187 | * 'saved_spsr_el3' - temporary copy to allow S-EL1 interrupt handling when |
| 188 | * the TSP has been preempted. |
| 189 | * 'saved_elr_el3' - temporary copy to allow S-EL1 interrupt handling when |
| 190 | * the TSP has been preempted. |
Achin Gupta | aeaab68 | 2014-05-09 13:21:31 +0100 | [diff] [blame] | 191 | * 'state' - collection of flags to track SP state e.g. on/off |
| 192 | * 'mpidr' - mpidr to associate a context with a cpu |
| 193 | * 'c_rt_ctx' - stack address to restore C runtime context from after |
| 194 | * returning from a synchronous entry into the SP. |
| 195 | * 'cpu_ctx' - space to maintain SP architectural state |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 196 | * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations |
| 197 | * which will queried using the TSP_GET_ARGS SMC by TSP. |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 198 | * 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved |
| 199 | * register context after it has been preempted by an EL3 |
| 200 | * routed NS interrupt and when a Secure Interrupt is taken |
| 201 | * to SP. |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 202 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 203 | typedef struct tsp_context { |
Achin Gupta | aeaab68 | 2014-05-09 13:21:31 +0100 | [diff] [blame] | 204 | uint64_t saved_elr_el3; |
| 205 | uint32_t saved_spsr_el3; |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 206 | uint32_t state; |
| 207 | uint64_t mpidr; |
| 208 | uint64_t c_rt_ctx; |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 209 | cpu_context_t cpu_ctx; |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 210 | uint64_t saved_tsp_args[TSP_NUM_ARGS]; |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 211 | #if TSP_NS_INTR_ASYNC_PREEMPT |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 212 | sp_ctx_regs_t sp_ctx; |
| 213 | #endif |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 214 | } tsp_context_t; |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 215 | |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 216 | /* Helper macros to store and retrieve tsp args from tsp_context */ |
| 217 | #define store_tsp_args(tsp_ctx, x1, x2) do {\ |
| 218 | tsp_ctx->saved_tsp_args[0] = x1;\ |
| 219 | tsp_ctx->saved_tsp_args[1] = x2;\ |
| 220 | } while (0) |
| 221 | |
| 222 | #define get_tsp_args(tsp_ctx, x1, x2) do {\ |
| 223 | x1 = tsp_ctx->saved_tsp_args[0];\ |
| 224 | x2 = tsp_ctx->saved_tsp_args[1];\ |
| 225 | } while (0) |
| 226 | |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 227 | /* TSPD power management handlers */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 228 | extern const spd_pm_ops_t tspd_pm; |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 229 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 230 | /******************************************************************************* |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 231 | * Forward declarations |
| 232 | ******************************************************************************/ |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 233 | struct tsp_vectors; |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 234 | |
| 235 | /******************************************************************************* |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 236 | * Function & Data prototypes |
| 237 | ******************************************************************************/ |
Dan Handley | a17fefa | 2014-05-14 12:38:32 +0100 | [diff] [blame] | 238 | uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); |
| 239 | void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); |
| 240 | uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); |
| 241 | void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 242 | void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep, |
| 243 | uint32_t rw, |
| 244 | uint64_t pc, |
| 245 | tsp_context_t *tsp_ctx); |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 246 | int tspd_abort_preempted_smc(tsp_context_t *tsp_ctx); |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 247 | |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 248 | extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 249 | extern struct tsp_vectors *tsp_vectors; |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 250 | #endif /*__ASSEMBLY__*/ |
| 251 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 252 | #endif /* __TSPD_PRIVATE_H__ */ |