Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
Maksims Svecovs | 3c0edf8 | 2023-04-20 14:44:53 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/debug.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 10 | #include <cortex_a72.h> |
| 11 | #include <cpu_macros.S> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable all types of L2 prefetches. |
| 15 | * --------------------------------------------- |
| 16 | */ |
| 17 | func cortex_a72_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 18 | ldcopr16 r0, r1, CORTEX_A72_ECTLR |
| 19 | orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 20 | bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ |
| 21 | CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) |
| 22 | stcopr16 r0, r1, CORTEX_A72_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 23 | isb |
| 24 | bx lr |
| 25 | endfunc cortex_a72_disable_l2_prefetch |
| 26 | |
| 27 | /* --------------------------------------------- |
| 28 | * Disable the load-store hardware prefetcher. |
| 29 | * --------------------------------------------- |
| 30 | */ |
| 31 | func cortex_a72_disable_hw_prefetcher |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 32 | ldcopr16 r0, r1, CORTEX_A72_CPUACTLR |
| 33 | orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH |
| 34 | stcopr16 r0, r1, CORTEX_A72_CPUACTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 35 | isb |
| 36 | dsb ish |
| 37 | bx lr |
| 38 | endfunc cortex_a72_disable_hw_prefetcher |
| 39 | |
| 40 | /* --------------------------------------------- |
| 41 | * Disable intra-cluster coherency |
| 42 | * Clobbers: r0-r1 |
| 43 | * --------------------------------------------- |
| 44 | */ |
| 45 | func cortex_a72_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 46 | ldcopr16 r0, r1, CORTEX_A72_ECTLR |
| 47 | bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT |
| 48 | stcopr16 r0, r1, CORTEX_A72_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 49 | bx lr |
| 50 | endfunc cortex_a72_disable_smp |
| 51 | |
| 52 | /* --------------------------------------------- |
| 53 | * Disable debug interfaces |
| 54 | * --------------------------------------------- |
| 55 | */ |
| 56 | func cortex_a72_disable_ext_debug |
| 57 | mov r0, #1 |
| 58 | stcopr r0, DBGOSDLR |
| 59 | isb |
| 60 | dsb sy |
| 61 | bx lr |
| 62 | endfunc cortex_a72_disable_ext_debug |
| 63 | |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 64 | /* --------------------------------------------------- |
| 65 | * Errata Workaround for Cortex A72 Errata #859971. |
| 66 | * This applies only to revision <= r0p3 of Cortex A72. |
| 67 | * Inputs: |
| 68 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 69 | * Shall clobber: r0-r3 |
| 70 | * --------------------------------------------------- |
| 71 | */ |
| 72 | func errata_a72_859971_wa |
| 73 | mov r2,lr |
| 74 | bl check_errata_859971 |
| 75 | mov lr, r2 |
| 76 | cmp r0, #ERRATA_NOT_APPLIES |
| 77 | beq 1f |
| 78 | ldcopr16 r0, r1, CORTEX_A72_CPUACTLR |
| 79 | orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH |
| 80 | stcopr16 r0, r1, CORTEX_A72_CPUACTLR |
| 81 | 1: |
| 82 | bx lr |
| 83 | endfunc errata_a72_859971_wa |
| 84 | |
| 85 | func check_errata_859971 |
| 86 | mov r1, #0x03 |
| 87 | b cpu_rev_var_ls |
| 88 | endfunc check_errata_859971 |
| 89 | |
Maksims Svecovs | 3c0edf8 | 2023-04-20 14:44:53 +0100 | [diff] [blame] | 90 | add_erratum_entry cortex_a72, ERRATUM(859971), ERRATA_A72_859971 |
| 91 | |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 92 | func check_errata_cve_2017_5715 |
| 93 | mov r0, #ERRATA_MISSING |
| 94 | bx lr |
| 95 | endfunc check_errata_cve_2017_5715 |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 96 | |
Maksims Svecovs | 3c0edf8 | 2023-04-20 14:44:53 +0100 | [diff] [blame] | 97 | add_erratum_entry cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 98 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 99 | func check_errata_cve_2018_3639 |
| 100 | #if WORKAROUND_CVE_2018_3639 |
| 101 | mov r0, #ERRATA_APPLIES |
| 102 | #else |
| 103 | mov r0, #ERRATA_MISSING |
| 104 | #endif |
| 105 | bx lr |
| 106 | endfunc check_errata_cve_2018_3639 |
| 107 | |
Maksims Svecovs | 3c0edf8 | 2023-04-20 14:44:53 +0100 | [diff] [blame] | 108 | add_erratum_entry cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 109 | |
John Powell | 7550aa2 | 2022-04-20 15:27:33 -0500 | [diff] [blame] | 110 | func check_errata_cve_2022_23960 |
| 111 | mov r0, #ERRATA_MISSING |
| 112 | bx lr |
| 113 | endfunc check_errata_cve_2022_23960 |
| 114 | |
Maksims Svecovs | 3c0edf8 | 2023-04-20 14:44:53 +0100 | [diff] [blame] | 115 | add_erratum_entry cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 116 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 117 | /* ------------------------------------------------- |
| 118 | * The CPU Ops reset function for Cortex-A72. |
| 119 | * ------------------------------------------------- |
| 120 | */ |
| 121 | func cortex_a72_reset_func |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 122 | mov r5, lr |
| 123 | bl cpu_get_rev_var |
| 124 | mov r4, r0 |
| 125 | |
| 126 | #if ERRATA_A72_859971 |
| 127 | mov r0, r4 |
| 128 | bl errata_a72_859971_wa |
| 129 | #endif |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 130 | |
| 131 | #if WORKAROUND_CVE_2018_3639 |
| 132 | ldcopr16 r0, r1, CORTEX_A72_CPUACTLR |
| 133 | orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE |
| 134 | stcopr16 r0, r1, CORTEX_A72_CPUACTLR |
| 135 | isb |
| 136 | dsb sy |
| 137 | #endif |
| 138 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 139 | /* --------------------------------------------- |
| 140 | * Enable the SMP bit. |
| 141 | * --------------------------------------------- |
| 142 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 143 | ldcopr16 r0, r1, CORTEX_A72_ECTLR |
| 144 | orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT |
| 145 | stcopr16 r0, r1, CORTEX_A72_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 146 | isb |
Manoj Kumar | e37c029 | 2018-01-19 17:51:31 +0530 | [diff] [blame] | 147 | bx r5 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 148 | endfunc cortex_a72_reset_func |
| 149 | |
| 150 | /* ---------------------------------------------------- |
| 151 | * The CPU Ops core power down function for Cortex-A72. |
| 152 | * ---------------------------------------------------- |
| 153 | */ |
| 154 | func cortex_a72_core_pwr_dwn |
| 155 | push {r12, lr} |
| 156 | |
| 157 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 158 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 159 | ldcopr r0, SCTLR |
| 160 | tst r0, #SCTLR_C_BIT |
| 161 | ASM_ASSERT(eq) |
| 162 | #endif |
| 163 | |
| 164 | /* --------------------------------------------- |
| 165 | * Disable the L2 prefetches. |
| 166 | * --------------------------------------------- |
| 167 | */ |
| 168 | bl cortex_a72_disable_l2_prefetch |
| 169 | |
| 170 | /* --------------------------------------------- |
| 171 | * Disable the load-store hardware prefetcher. |
| 172 | * --------------------------------------------- |
| 173 | */ |
| 174 | bl cortex_a72_disable_hw_prefetcher |
| 175 | |
| 176 | /* --------------------------------------------- |
| 177 | * Flush L1 caches. |
| 178 | * --------------------------------------------- |
| 179 | */ |
| 180 | mov r0, #DC_OP_CISW |
| 181 | bl dcsw_op_level1 |
| 182 | |
| 183 | /* --------------------------------------------- |
| 184 | * Come out of intra cluster coherency |
| 185 | * --------------------------------------------- |
| 186 | */ |
| 187 | bl cortex_a72_disable_smp |
| 188 | |
| 189 | /* --------------------------------------------- |
| 190 | * Force the debug interfaces to be quiescent |
| 191 | * --------------------------------------------- |
| 192 | */ |
| 193 | pop {r12, lr} |
| 194 | b cortex_a72_disable_ext_debug |
| 195 | endfunc cortex_a72_core_pwr_dwn |
| 196 | |
| 197 | /* ------------------------------------------------------- |
| 198 | * The CPU Ops cluster power down function for Cortex-A72. |
| 199 | * ------------------------------------------------------- |
| 200 | */ |
| 201 | func cortex_a72_cluster_pwr_dwn |
| 202 | push {r12, lr} |
| 203 | |
| 204 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 205 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 206 | ldcopr r0, SCTLR |
| 207 | tst r0, #SCTLR_C_BIT |
| 208 | ASM_ASSERT(eq) |
| 209 | #endif |
| 210 | |
| 211 | /* --------------------------------------------- |
| 212 | * Disable the L2 prefetches. |
| 213 | * --------------------------------------------- |
| 214 | */ |
| 215 | bl cortex_a72_disable_l2_prefetch |
| 216 | |
| 217 | /* --------------------------------------------- |
| 218 | * Disable the load-store hardware prefetcher. |
| 219 | * --------------------------------------------- |
| 220 | */ |
| 221 | bl cortex_a72_disable_hw_prefetcher |
| 222 | |
| 223 | #if !SKIP_A72_L1_FLUSH_PWR_DWN |
| 224 | /* --------------------------------------------- |
| 225 | * Flush L1 caches. |
| 226 | * --------------------------------------------- |
| 227 | */ |
| 228 | mov r0, #DC_OP_CISW |
| 229 | bl dcsw_op_level1 |
| 230 | #endif |
| 231 | |
| 232 | /* --------------------------------------------- |
| 233 | * Disable the optional ACP. |
| 234 | * --------------------------------------------- |
| 235 | */ |
| 236 | bl plat_disable_acp |
| 237 | |
| 238 | /* ------------------------------------------------- |
| 239 | * Flush the L2 caches. |
| 240 | * ------------------------------------------------- |
| 241 | */ |
| 242 | mov r0, #DC_OP_CISW |
| 243 | bl dcsw_op_level2 |
| 244 | |
| 245 | /* --------------------------------------------- |
| 246 | * Come out of intra cluster coherency |
| 247 | * --------------------------------------------- |
| 248 | */ |
| 249 | bl cortex_a72_disable_smp |
| 250 | |
| 251 | /* --------------------------------------------- |
| 252 | * Force the debug interfaces to be quiescent |
| 253 | * --------------------------------------------- |
| 254 | */ |
| 255 | pop {r12, lr} |
| 256 | b cortex_a72_disable_ext_debug |
| 257 | endfunc cortex_a72_cluster_pwr_dwn |
| 258 | |
Maksims Svecovs | 3c0edf8 | 2023-04-20 14:44:53 +0100 | [diff] [blame] | 259 | errata_report_shim cortex_a72 |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 260 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 261 | declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ |
| 262 | cortex_a72_reset_func, \ |
| 263 | cortex_a72_core_pwr_dwn, \ |
| 264 | cortex_a72_cluster_pwr_dwn |