johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a710.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 24 | /* -------------------------------------------------- |
| 25 | * Errata Workaround for Cortex-A710 Erratum 1987031. |
| 26 | * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still |
| 27 | * open. |
| 28 | * Inputs: |
| 29 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 30 | * Shall clobber: x0-x17 |
| 31 | * -------------------------------------------------- |
| 32 | */ |
| 33 | func errata_a710_1987031_wa |
| 34 | /* Check revision. */ |
| 35 | mov x17, x30 |
| 36 | bl check_errata_1987031 |
| 37 | cbz x0, 1f |
| 38 | |
| 39 | /* Apply instruction patching sequence */ |
| 40 | ldr x0,=0x6 |
| 41 | msr S3_6_c15_c8_0,x0 |
| 42 | ldr x0,=0xF3A08002 |
| 43 | msr S3_6_c15_c8_2,x0 |
| 44 | ldr x0,=0xFFF0F7FE |
| 45 | msr S3_6_c15_c8_3,x0 |
| 46 | ldr x0,=0x40000001003ff |
| 47 | msr S3_6_c15_c8_1,x0 |
| 48 | ldr x0,=0x7 |
| 49 | msr S3_6_c15_c8_0,x0 |
| 50 | ldr x0,=0xBF200000 |
| 51 | msr S3_6_c15_c8_2,x0 |
| 52 | ldr x0,=0xFFEF0000 |
| 53 | msr S3_6_c15_c8_3,x0 |
| 54 | ldr x0,=0x40000001003f3 |
| 55 | msr S3_6_c15_c8_1,x0 |
| 56 | isb |
| 57 | 1: |
| 58 | ret x17 |
| 59 | endfunc errata_a710_1987031_wa |
| 60 | |
| 61 | func check_errata_1987031 |
| 62 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 63 | mov x1, #0x20 |
| 64 | b cpu_rev_var_ls |
| 65 | endfunc check_errata_1987031 |
| 66 | |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 67 | /* -------------------------------------------------- |
| 68 | * Errata Workaround for Cortex-A710 Erratum 2081180. |
| 69 | * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. |
| 70 | * It is still open. |
| 71 | * Inputs: |
| 72 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 73 | * Shall clobber: x0-x17 |
| 74 | * -------------------------------------------------- |
| 75 | */ |
| 76 | func errata_a710_2081180_wa |
| 77 | /* Check revision. */ |
| 78 | mov x17, x30 |
| 79 | bl check_errata_2081180 |
| 80 | cbz x0, 1f |
| 81 | |
| 82 | /* Apply instruction patching sequence */ |
| 83 | ldr x0,=0x3 |
| 84 | msr S3_6_c15_c8_0,x0 |
| 85 | ldr x0,=0xF3A08002 |
| 86 | msr S3_6_c15_c8_2,x0 |
| 87 | ldr x0,=0xFFF0F7FE |
| 88 | msr S3_6_c15_c8_3,x0 |
| 89 | ldr x0,=0x10002001003FF |
| 90 | msr S3_6_c15_c8_1,x0 |
| 91 | ldr x0,=0x4 |
| 92 | msr S3_6_c15_c8_0,x0 |
| 93 | ldr x0,=0xBF200000 |
| 94 | msr S3_6_c15_c8_2,x0 |
| 95 | ldr x0,=0xFFEF0000 |
| 96 | msr S3_6_c15_c8_3,x0 |
| 97 | ldr x0,=0x10002001003F3 |
| 98 | msr S3_6_c15_c8_1,x0 |
| 99 | isb |
| 100 | 1: |
| 101 | ret x17 |
| 102 | endfunc errata_a710_2081180_wa |
| 103 | |
| 104 | func check_errata_2081180 |
| 105 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 106 | mov x1, #0x20 |
| 107 | b cpu_rev_var_ls |
| 108 | endfunc check_errata_2081180 |
| 109 | |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 110 | /* --------------------------------------------------------------------- |
| 111 | * Errata Workaround for Cortex-A710 Erratum 2055002. |
| 112 | * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. |
| 113 | * Inputs: |
| 114 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 115 | * Shall clobber: x0-x17 |
| 116 | * --------------------------------------------------------------------- |
| 117 | */ |
| 118 | func errata_a710_2055002_wa |
| 119 | /* Compare x0 against revision r2p0 */ |
| 120 | mov x17, x30 |
| 121 | bl check_errata_2055002 |
| 122 | cbz x0, 1f |
| 123 | mrs x1, CORTEX_A710_CPUACTLR_EL1 |
| 124 | orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 |
| 125 | msr CORTEX_A710_CPUACTLR_EL1, x1 |
| 126 | 1: |
| 127 | ret x17 |
| 128 | endfunc errata_a710_2055002_wa |
| 129 | |
| 130 | func check_errata_2055002 |
| 131 | /* Applies to r1p0, r2p0 */ |
| 132 | mov x1, #0x20 |
| 133 | b cpu_rev_var_ls |
| 134 | endfunc check_errata_2055002 |
| 135 | |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 136 | /* ------------------------------------------------------------- |
| 137 | * Errata Workaround for Cortex-A710 Erratum 2017096. |
| 138 | * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. |
| 139 | * Inputs: |
| 140 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 141 | * Shall clobber: x0-x17 |
| 142 | * ------------------------------------------------------------- |
| 143 | */ |
| 144 | func errata_a710_2017096_wa |
| 145 | /* Compare x0 against revision r0p0 to r2p0 */ |
| 146 | mov x17, x30 |
| 147 | bl check_errata_2017096 |
| 148 | cbz x0, 1f |
| 149 | mrs x1, CORTEX_A710_CPUECTLR_EL1 |
| 150 | orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT |
| 151 | msr CORTEX_A710_CPUECTLR_EL1, x1 |
| 152 | |
| 153 | 1: |
| 154 | ret x17 |
| 155 | endfunc errata_a710_2017096_wa |
| 156 | |
| 157 | func check_errata_2017096 |
| 158 | /* Applies to r0p0, r1p0, r2p0 */ |
| 159 | mov x1, #0x20 |
| 160 | b cpu_rev_var_ls |
| 161 | endfunc check_errata_2017096 |
| 162 | |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 163 | |
| 164 | /* --------------------------------------------------------------------- |
| 165 | * Errata Workaround for Cortex-A710 Erratum 2083908. |
| 166 | * This applies to revision r2p0 of Cortex-A710 and is still open. |
| 167 | * Inputs: |
| 168 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 169 | * Shall clobber: x0-x17 |
| 170 | * --------------------------------------------------------------------- |
| 171 | */ |
| 172 | func errata_a710_2083908_wa |
| 173 | /* Compare x0 against revision r2p0 */ |
| 174 | mov x17, x30 |
| 175 | bl check_errata_2083908 |
| 176 | cbz x0, 1f |
| 177 | mrs x1, CORTEX_A710_CPUACTLR5_EL1 |
| 178 | orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 |
| 179 | msr CORTEX_A710_CPUACTLR5_EL1, x1 |
| 180 | 1: |
| 181 | ret x17 |
| 182 | endfunc errata_a710_2083908_wa |
| 183 | |
| 184 | func check_errata_2083908 |
| 185 | /* Applies to r2p0 */ |
| 186 | mov x1, #CPU_REV(2, 0) |
| 187 | mov x2, #CPU_REV(2, 0) |
| 188 | b cpu_rev_var_range |
| 189 | endfunc check_errata_2083908 |
| 190 | |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 191 | /* --------------------------------------------------------------------- |
| 192 | * Errata Workaround for Cortex-A710 Erratum 2058056. |
| 193 | * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still |
| 194 | * open. |
| 195 | * Inputs: |
| 196 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 197 | * Shall clobber: x0-x17 |
| 198 | * --------------------------------------------------------------------- |
| 199 | */ |
| 200 | func errata_a710_2058056_wa |
| 201 | /* Compare x0 against revision r2p0 */ |
| 202 | mov x17, x30 |
| 203 | bl check_errata_2058056 |
| 204 | cbz x0, 1f |
| 205 | mrs x1, CORTEX_A710_CPUECTLR2_EL1 |
| 206 | mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV |
| 207 | bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH |
| 208 | msr CORTEX_A710_CPUECTLR2_EL1, x1 |
| 209 | 1: |
| 210 | ret x17 |
| 211 | endfunc errata_a710_2058056_wa |
| 212 | |
| 213 | func check_errata_2058056 |
| 214 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 215 | mov x1, #0x20 |
| 216 | b cpu_rev_var_ls |
| 217 | endfunc check_errata_2058056 |
| 218 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 219 | /* ---------------------------------------------------- |
| 220 | * HW will do the cache maintenance while powering down |
| 221 | * ---------------------------------------------------- |
| 222 | */ |
| 223 | func cortex_a710_core_pwr_dwn |
| 224 | /* --------------------------------------------------- |
| 225 | * Enable CPU power down bit in power control register |
| 226 | * --------------------------------------------------- |
| 227 | */ |
| 228 | mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 |
| 229 | orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 230 | msr CORTEX_A710_CPUPWRCTLR_EL1, x0 |
| 231 | isb |
| 232 | ret |
| 233 | endfunc cortex_a710_core_pwr_dwn |
| 234 | |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 235 | #if REPORT_ERRATA |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 236 | /* |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 237 | * Errata printing function for Cortex-A710. Must follow AAPCS. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 238 | */ |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 239 | func cortex_a710_errata_report |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 240 | stp x8, x30, [sp, #-16]! |
| 241 | |
| 242 | bl cpu_get_rev_var |
| 243 | mov x8, x0 |
| 244 | |
| 245 | /* |
| 246 | * Report all errata. The revision-variant information is passed to |
| 247 | * checking functions of each errata. |
| 248 | */ |
| 249 | report_errata ERRATA_A710_1987031, cortex_a710, 1987031 |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 250 | report_errata ERRATA_A710_2081180, cortex_a710, 2081180 |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 251 | report_errata ERRATA_A710_2055002, cortex_a710, 2055002 |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 252 | report_errata ERRATA_A710_2017096, cortex_a710, 2017096 |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 253 | report_errata ERRATA_A710_2083908, cortex_a710, 2083908 |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 254 | report_errata ERRATA_A710_2058056, cortex_a710, 2058056 |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 255 | |
| 256 | ldp x8, x30, [sp], #16 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 257 | ret |
| 258 | endfunc cortex_a710_errata_report |
| 259 | #endif |
| 260 | |
| 261 | func cortex_a710_reset_func |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 262 | mov x19, x30 |
| 263 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 264 | /* Disable speculative loads */ |
| 265 | msr SSBS, xzr |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 266 | |
| 267 | bl cpu_get_rev_var |
| 268 | mov x18, x0 |
| 269 | |
| 270 | #if ERRATA_A710_1987031 |
| 271 | mov x0, x18 |
| 272 | bl errata_a710_1987031_wa |
| 273 | #endif |
| 274 | |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 275 | #if ERRATA_A710_2081180 |
| 276 | mov x0, x18 |
| 277 | bl errata_a710_2081180_wa |
| 278 | #endif |
| 279 | |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 280 | #if ERRATA_A710_2055002 |
| 281 | mov x0, x18 |
| 282 | bl errata_a710_2055002_wa |
| 283 | #endif |
| 284 | |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 285 | #if ERRATA_A710_2017096 |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 286 | mov x0, x18 |
| 287 | bl errata_a710_2017096_wa |
| 288 | #endif |
| 289 | |
| 290 | #if ERRATA_A710_2083908 |
| 291 | mov x0, x18 |
| 292 | bl errata_a710_2083908_wa |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 293 | #endif |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 294 | |
| 295 | #if ERRATA_A710_2058056 |
| 296 | mov x0, x18 |
| 297 | bl errata_a710_2058056_wa |
| 298 | #endif |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 299 | isb |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 300 | ret x19 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 301 | endfunc cortex_a710_reset_func |
| 302 | |
| 303 | /* --------------------------------------------- |
| 304 | * This function provides Cortex-A710 specific |
| 305 | * register information for crash reporting. |
| 306 | * It needs to return with x6 pointing to |
| 307 | * a list of register names in ascii and |
| 308 | * x8 - x15 having values of registers to be |
| 309 | * reported. |
| 310 | * --------------------------------------------- |
| 311 | */ |
| 312 | .section .rodata.cortex_a710_regs, "aS" |
| 313 | cortex_a710_regs: /* The ascii list of register names to be reported */ |
| 314 | .asciz "cpuectlr_el1", "" |
| 315 | |
| 316 | func cortex_a710_cpu_reg_dump |
| 317 | adr x6, cortex_a710_regs |
| 318 | mrs x8, CORTEX_A710_CPUECTLR_EL1 |
| 319 | ret |
| 320 | endfunc cortex_a710_cpu_reg_dump |
| 321 | |
| 322 | declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ |
| 323 | cortex_a710_reset_func, \ |
| 324 | cortex_a710_core_pwr_dwn |