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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
7#ifndef __PLAT_MACROS_S__
8#define __PLAT_MACROS_S__
9
10#include <gic_v2.h>
11#include <tegra_def.h>
12
13.section .rodata.gic_reg_name, "aS"
14gicc_regs:
15 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
16gicd_pend_reg:
17 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
18newline:
19 .asciz "\n"
20spacer:
21 .asciz ":\t\t0x"
22
23/* ---------------------------------------------
24 * The below macro prints out relevant GIC
25 * registers whenever an unhandled exception is
26 * taken in BL31.
27 * ---------------------------------------------
28 */
Gerald Lejeune2c7ed5b2015-11-26 15:47:53 +010029.macro plat_crash_print_regs
Varun Wadekarb316e242015-05-19 16:48:04 +053030 mov_imm x16, TEGRA_GICC_BASE
Varun Wadekarbfc66052016-08-23 14:01:19 -070031
Varun Wadekarb316e242015-05-19 16:48:04 +053032 /* gicc base address is now in x16 */
33 adr x6, gicc_regs /* Load the gicc reg list to x6 */
34 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
35 ldr w8, [x16, #GICC_HPPIR]
36 ldr w9, [x16, #GICC_AHPPIR]
37 ldr w10, [x16, #GICC_CTLR]
38 /* Store to the crash buf and print to cosole */
39 bl str_in_crash_buf_print
40
41 /* Print the GICD_ISPENDR regs */
Varun Wadekarbfc66052016-08-23 14:01:19 -070042 mov_imm x16, TEGRA_GICD_BASE
Varun Wadekarb316e242015-05-19 16:48:04 +053043 add x7, x16, #GICD_ISPENDR
44 adr x4, gicd_pend_reg
45 bl asm_print_str
462:
47 sub x4, x7, x16
48 cmp x4, #0x280
49 b.eq 1f
50 bl asm_print_hex
51 adr x4, spacer
52 bl asm_print_str
53 ldr x4, [x7], #8
54 bl asm_print_hex
55 adr x4, newline
56 bl asm_print_str
57 b 2b
581:
59.endm
60
Varun Wadekarb316e242015-05-19 16:48:04 +053061#endif /* __PLAT_MACROS_S__ */