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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Dan Handley6fa89a22018-02-27 16:03:58 +00002# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
13# The AArch32 Secure Payload to be built as BL32 image
14AARCH32_SP := none
15
16# The Target build architecture. Supported values are: aarch64, aarch32.
17ARCH := aarch64
18
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000019# ARM Architecture major and minor versions: 8.0 by default.
20ARM_ARCH_MAJOR := 8
21ARM_ARCH_MINOR := 0
22
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010023# Determine the version of ARM GIC architecture to use for interrupt management
24# in EL3. The platform port can change this value if needed.
25ARM_GIC_ARCH := 2
26
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010027# Base commit to perform code check on
28BASE_COMMIT := origin/master
29
Roberto Vargase0e99462017-10-30 14:43:43 +000030# Execute BL2 at EL3
31BL2_AT_EL3 := 0
32
Jiafei Pan43a7bf42018-03-21 07:20:09 +000033# BL2 image is stored in XIP memory, for now, this option is only supported
34# when BL2_AT_EL3 is 1.
35BL2_IN_XIP_MEM := 0
36
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010037# By default, consider that the platform may release several CPUs out of reset.
38# The platform Makefile is free to override this value.
39COLD_BOOT_SINGLE_CPU := 0
40
Julius Wernerb624ae02017-06-09 15:17:15 -070041# Flag to compile in coreboot support code. Exclude by default. The coreboot
42# Makefile system will set this when compiling TF as part of a coreboot image.
43COREBOOT := 0
44
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010045# For Chain of Trust
46CREATE_KEYS := 1
47
48# Build flag to include AArch32 registers in cpu context save and restore during
49# world switch. This flag must be set to 0 for AArch64-only platforms.
50CTX_INCLUDE_AARCH32_REGS := 1
51
52# Include FP registers in cpu context
53CTX_INCLUDE_FPREGS := 0
54
55# Debug build
56DEBUG := 0
57
58# Build platform
59DEFAULT_PLAT := fvp
60
Soby Mathew9fe88042018-03-26 12:43:37 +010061# Enable capability to disable authentication dynamically. Only meant for
62# development platforms.
63DYN_DISABLE_AUTH := 0
64
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010065# Flag to enable Performance Measurement Framework
66ENABLE_PMF := 0
67
68# Flag to enable PSCI STATs functionality
69ENABLE_PSCI_STAT := 0
70
71# Flag to enable runtime instrumentation using PMF
72ENABLE_RUNTIME_INSTRUMENTATION := 0
73
Douglas Raillard306593d2017-02-24 18:14:15 +000074# Flag to enable stack corruption protection
75ENABLE_STACK_PROTECTOR := 0
76
Jeenu Viswambharan10a67272017-09-22 08:32:10 +010077# Flag to enable exception handling in EL3
78EL3_EXCEPTION_HANDLING := 0
79
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010080# Build flag to treat usage of deprecated platform and framework APIs as error.
81ERROR_DEPRECATED := 0
82
Jeenu Viswambharanf00da742017-12-08 12:13:51 +000083# Fault injection support
84FAULT_INJECTION_SUPPORT := 0
85
Masahiro Yamada4d87eb42016-12-25 13:52:22 +090086# Byte alignment that each component in FIP is aligned to
87FIP_ALIGN := 0
88
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010089# Default FIP file name
90FIP_NAME := fip.bin
91
92# Default FWU_FIP file name
93FWU_FIP_NAME := fwu_fip.bin
94
95# For Chain of Trust
96GENERATE_COT := 0
97
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010098# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
99# default, they are for Secure EL1.
100GICV2_G0_FOR_EL3 := 0
101
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000102# Route External Aborts to EL3. Disabled by default; External Aborts are handled
103# by lower ELs.
104HANDLE_EA_EL3_FIRST := 0
105
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000106# Whether system coherency is managed in hardware, without explicit software
107# operations.
108HW_ASSISTED_COHERENCY := 0
109
Soby Mathew13b16052017-08-31 11:49:32 +0100110# Set the default algorithm for the generation of Trusted Board Boot keys
111KEY_ALG := rsa
112
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100113# Flag to enable new version of image loading
114LOAD_IMAGE_V2 := 0
115
Dan Handley6fa89a22018-02-27 16:03:58 +0000116# Enable use of the console API allowing multiple consoles to be registered
117# at the same time.
118MULTI_CONSOLE_API := 0
Julius Werner94f89072017-07-31 18:15:11 -0700119
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100120# NS timer register save and restore
121NS_TIMER_SWITCH := 0
122
123# Build PL011 UART driver in minimal generic UART mode
124PL011_GENERIC_UART := 0
125
126# By default, consider that the platform's reset address is not programmable.
127# The platform Makefile is free to override this value.
128PROGRAMMABLE_RESET_ADDRESS := 0
129
130# Flag used to choose the power state format viz Extended State-ID or the
131# Original format.
132PSCI_EXTENDED_STATE_ID := 0
133
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100134# Enable RAS support
135RAS_EXTENSION := 0
136
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100137# By default, BL1 acts as the reset handler, not BL31
138RESET_TO_BL31 := 0
139
140# For Chain of Trust
141SAVE_KEYS := 0
142
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100143# Software Delegated Exception support
144SDEI_SUPPORT := 0
145
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100146# Whether code and read-only data should be put on separate memory pages. The
147# platform Makefile is free to override this value.
148SEPARATE_CODE_AND_RODATA := 0
149
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100150# Default to SMCCC Version 1.X
151SMCCC_MAJOR_VERSION := 1
152
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100153# SPD choice
154SPD := none
155
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100156# For including the Secure Partition Manager
157ENABLE_SPM := 0
158
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100159# Flag to introduce an infinite loop in BL1 just before it exits into the next
160# image. This is meant to help debugging the post-BL2 phase.
161SPIN_ON_BL1_EXIT := 0
162
163# Flags to build TF with Trusted Boot support
164TRUSTED_BOARD_BOOT := 0
165
166# Build option to choose whether Trusted firmware uses Coherent memory or not.
167USE_COHERENT_MEM := 1
168
Roberto Vargase92111a2018-05-22 16:05:42 +0100169# Build option to choose wheter Trusted firmware uses library at ROM
170USE_ROMLIB := 0
171
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900172# Use tbbr_oid.h instead of platform_oid.h
173USE_TBBR_DEFS = $(ERROR_DEPRECATED)
174
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100175# Build verbosity
176V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100177
178# Whether to enable D-Cache early during warm boot. This is usually
179# applicable for platforms wherein interconnect programming is not
180# required to enable cache coherency after warm reset (eg: single cluster
181# platforms).
182WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100183
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100184# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100185ENABLE_SPE_FOR_LOWER_ELS := 1
186
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100187# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100188ifeq (${ARCH},aarch32)
189 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100190endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100191
192ENABLE_AMU := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100193
194# By default, enable Scalable Vector Extension if implemented for Non-secure
195# lower ELs
196# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
197ifneq (${ARCH},aarch32)
198 ENABLE_SVE_FOR_NS := 1
199else
200 override ENABLE_SVE_FOR_NS := 0
201endif