Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 31 | #include <platform.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <fvp_pwrc.h> |
| 33 | |
| 34 | /******************************************************************************* |
| 35 | * Declarations of linker defined symbols which will help us find the layout |
| 36 | * of trusted SRAM |
| 37 | ******************************************************************************/ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 38 | extern unsigned long __RO_START__; |
| 39 | extern unsigned long __RO_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 41 | extern unsigned long __COHERENT_RAM_START__; |
| 42 | extern unsigned long __COHERENT_RAM_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 43 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 44 | /* |
| 45 | * The next 2 constants identify the extents of the code & RO data region. |
| 46 | * These addresses are used by the MMU setup code and therefore they must be |
| 47 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 48 | * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. |
| 49 | */ |
| 50 | #define BL31_RO_BASE (unsigned long)(&__RO_START__) |
| 51 | #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) |
| 52 | |
| 53 | /* |
| 54 | * The next 2 constants identify the extents of the coherent memory region. |
| 55 | * These addresses are used by the MMU setup code and therefore they must be |
| 56 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 57 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols |
| 58 | * refer to page-aligned addresses. |
| 59 | */ |
| 60 | #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 61 | #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 62 | |
| 63 | /******************************************************************************* |
Sandrine Bailleux | 93ca221 | 2013-12-02 15:57:09 +0000 | [diff] [blame] | 64 | * This data structure holds information copied by BL31 from BL2 to pass |
| 65 | * control to the normal world software images. |
| 66 | * TODO: Can this be moved out of device memory. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 67 | ******************************************************************************/ |
Sandrine Bailleux | 93ca221 | 2013-12-02 15:57:09 +0000 | [diff] [blame] | 68 | static el_change_info ns_entry_info |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 69 | __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), |
Sandrine Bailleux | 204aa03 | 2013-10-28 15:14:00 +0000 | [diff] [blame] | 70 | section("tzfw_coherent_mem"))); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 71 | |
| 72 | /* Data structure which holds the extents of the trusted SRAM for BL31 */ |
| 73 | static meminfo bl31_tzram_layout |
| 74 | __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), |
Sandrine Bailleux | 204aa03 | 2013-10-28 15:14:00 +0000 | [diff] [blame] | 75 | section("tzfw_coherent_mem"))); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 76 | |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 77 | meminfo *bl31_plat_sec_mem_layout(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 78 | { |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 79 | return &bl31_tzram_layout; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | /******************************************************************************* |
| 83 | * Return information about passing control to the non-trusted software images |
| 84 | * to common code.TODO: In the initial architecture, the image after BL31 will |
| 85 | * always run in the non-secure state. In the final architecture there |
| 86 | * will be a series of images. This function will need enhancement then |
| 87 | ******************************************************************************/ |
Sandrine Bailleux | 93ca221 | 2013-12-02 15:57:09 +0000 | [diff] [blame] | 88 | el_change_info *bl31_get_next_image_info(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 89 | { |
Sandrine Bailleux | 93ca221 | 2013-12-02 15:57:09 +0000 | [diff] [blame] | 90 | return &ns_entry_info; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | /******************************************************************************* |
| 94 | * Perform any BL31 specific platform actions. Here we copy parameters passed |
| 95 | * by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they are lost |
| 96 | * (potentially). This is done before the MMU is initialized so that the memory |
| 97 | * layout can be used while creating page tables. |
| 98 | ******************************************************************************/ |
| 99 | void bl31_early_platform_setup(meminfo *mem_layout, |
Sandrine Bailleux | 93ca221 | 2013-12-02 15:57:09 +0000 | [diff] [blame] | 100 | void *data) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | { |
| 102 | el_change_info *image_info = (el_change_info *) data; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 103 | |
| 104 | /* Setup the BL31 memory layout */ |
| 105 | bl31_tzram_layout.total_base = mem_layout->total_base; |
| 106 | bl31_tzram_layout.total_size = mem_layout->total_size; |
| 107 | bl31_tzram_layout.free_base = mem_layout->free_base; |
| 108 | bl31_tzram_layout.free_size = mem_layout->free_size; |
| 109 | bl31_tzram_layout.attr = mem_layout->attr; |
| 110 | bl31_tzram_layout.next = 0; |
| 111 | |
Sandrine Bailleux | 93ca221 | 2013-12-02 15:57:09 +0000 | [diff] [blame] | 112 | /* Save information about jumping into the normal world */ |
| 113 | ns_entry_info.entrypoint = image_info->entrypoint; |
| 114 | ns_entry_info.spsr = image_info->spsr; |
| 115 | ns_entry_info.args = image_info->args; |
| 116 | ns_entry_info.security_state = image_info->security_state; |
| 117 | ns_entry_info.next = image_info->next; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 118 | |
| 119 | /* Initialize the platform config for future decision making */ |
| 120 | platform_config_setup(); |
| 121 | } |
| 122 | |
| 123 | /******************************************************************************* |
| 124 | * Initialize the gic, configure the CLCD and zero out variables needed by the |
| 125 | * secondaries to boot up correctly. |
| 126 | ******************************************************************************/ |
| 127 | void bl31_platform_setup() |
| 128 | { |
| 129 | unsigned int reg_val; |
| 130 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 131 | /* Initialize the gic cpu and distributor interfaces */ |
| 132 | gic_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * TODO: Configure the CLCD before handing control to |
| 136 | * linux. Need to see if a separate driver is needed |
| 137 | * instead. |
| 138 | */ |
| 139 | mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); |
| 140 | mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 141 | (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); |
| 142 | |
| 143 | /* Allow access to the System counter timer module */ |
| 144 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 145 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 146 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 147 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); |
| 148 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); |
| 149 | |
| 150 | reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); |
| 151 | mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 152 | |
| 153 | /* Intialize the power controller */ |
| 154 | fvp_pwrc_setup(); |
| 155 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 156 | /* Topologies are best known to the platform. */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 157 | plat_setup_topology(); |
| 158 | } |
| 159 | |
| 160 | /******************************************************************************* |
| 161 | * Perform the very early platform specific architectural setup here. At the |
| 162 | * moment this is only intializes the mmu in a quick and dirty way. |
| 163 | ******************************************************************************/ |
| 164 | void bl31_plat_arch_setup() |
| 165 | { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 166 | configure_mmu(&bl31_tzram_layout, |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 167 | BL31_RO_BASE, |
| 168 | BL31_RO_LIMIT, |
| 169 | BL31_COHERENT_RAM_BASE, |
| 170 | BL31_COHERENT_RAM_LIMIT); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | } |