johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
Harrison Mutai | e5249fe | 2022-12-09 12:14:25 +0000 | [diff] [blame] | 2 | * Copyright (c) 2023, Arm Limited. All rights reserved. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a510.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 16 | #error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 21 | #error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 22 | #endif |
| 23 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 24 | workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 25 | /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 26 | sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ |
| 27 | CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 28 | workaround_reset_end cortex_a510, ERRATUM(1922240) |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 29 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 30 | check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 31 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 32 | workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 |
johpow01 | 5a99300 | 2022-01-11 17:54:41 -0600 | [diff] [blame] | 33 | /* Apply workaround */ |
| 34 | mov x0, xzr |
| 35 | msr S3_6_C15_C4_0, x0 |
| 36 | isb |
| 37 | |
| 38 | mov x0, #0x8500000 |
| 39 | msr S3_6_C15_C4_2, x0 |
| 40 | |
| 41 | mov x0, #0x1F700000 |
| 42 | movk x0, #0x8, lsl #32 |
| 43 | msr S3_6_C15_C4_3, x0 |
| 44 | |
| 45 | mov x0, #0x3F1 |
| 46 | movk x0, #0x110, lsl #16 |
| 47 | msr S3_6_C15_C4_1, x0 |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 48 | workaround_reset_end cortex_a510, ERRATUM(2041909) |
johpow01 | 5a99300 | 2022-01-11 17:54:41 -0600 | [diff] [blame] | 49 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 50 | check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) |
johpow01 | 5a99300 | 2022-01-11 17:54:41 -0600 | [diff] [blame] | 51 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 52 | workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 53 | /* Apply the workaround by disabling ReadPreferUnique. */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 54 | sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ |
| 55 | CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 56 | workaround_reset_end cortex_a510, ERRATUM(2042739) |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 57 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 58 | check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 59 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 60 | workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 61 | /* |
| 62 | * Force L2 allocation of transient lines by setting |
| 63 | * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. |
| 64 | */ |
| 65 | mrs x0, CORTEX_A510_CPUECTLR_EL1 |
| 66 | mov x1, #1 |
| 67 | bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 |
| 68 | bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 |
| 69 | msr CORTEX_A510_CPUECTLR_EL1, x0 |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 70 | workaround_reset_end cortex_a510, ERRATUM(2172148) |
johpow01 | 3ba9cb2 | 2022-02-13 21:00:10 -0600 | [diff] [blame] | 71 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 72 | check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) |
johpow01 | 3ba9cb2 | 2022-02-13 21:00:10 -0600 | [diff] [blame] | 73 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 74 | workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 |
johpow01 | 3ead295 | 2022-02-14 20:19:08 -0600 | [diff] [blame] | 75 | /* Set bit 18 in CPUACTLR_EL1 */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 76 | sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ |
| 77 | CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH |
johpow01 | 3ead295 | 2022-02-14 20:19:08 -0600 | [diff] [blame] | 78 | |
| 79 | /* Set bit 25 in CMPXACTLR_EL1 */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 80 | sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ |
| 81 | CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH |
| 82 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 83 | workaround_reset_end cortex_a510, ERRATUM(2218950) |
johpow01 | 3ead295 | 2022-02-14 20:19:08 -0600 | [diff] [blame] | 84 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 85 | check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) |
johpow01 | 3ead295 | 2022-02-14 20:19:08 -0600 | [diff] [blame] | 86 | |
johpow01 | ac55c01 | 2022-02-15 22:55:22 -0600 | [diff] [blame] | 87 | /* -------------------------------------------------- |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 88 | * This workaround is not a typical errata fix. MPMM |
| 89 | * is disabled here, but this conflicts with the BL31 |
| 90 | * MPMM support. So in addition to simply disabling |
| 91 | * the feature, a flag is set in the MPMM library |
| 92 | * indicating that it should not be enabled even if |
| 93 | * ENABLE_MPMM=1. |
johpow01 | ac55c01 | 2022-02-15 22:55:22 -0600 | [diff] [blame] | 94 | * -------------------------------------------------- |
| 95 | */ |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 96 | workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 97 | /* Disable MPMM */ |
| 98 | mrs x0, CPUMPMMCR_EL3 |
| 99 | bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ |
| 100 | msr CPUMPMMCR_EL3, x0 |
| 101 | |
| 102 | #if ENABLE_MPMM && IMAGE_BL31 |
| 103 | /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ |
| 104 | bl mpmm_errata_disable |
| 105 | #endif |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 106 | workaround_reset_end cortex_a510, ERRATUM(2250311) |
johpow01 | ac55c01 | 2022-02-15 22:55:22 -0600 | [diff] [blame] | 107 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 108 | check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 109 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 110 | workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 111 | /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 112 | sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ |
| 113 | CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 114 | workaround_reset_end cortex_a510, ERRATUM(2288014) |
Jayanth Dodderi Chidanand | 16e5ca2 | 2023-04-11 11:42:53 +0100 | [diff] [blame] | 115 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 116 | check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) |
Akram Ahmad | a85254e | 2022-07-21 14:01:33 +0100 | [diff] [blame] | 117 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 118 | workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 |
Akram Ahmad | a85254e | 2022-07-21 14:01:33 +0100 | [diff] [blame] | 119 | /* |
| 120 | * Set CPUACTLR_EL1[17] to 1'b1, which disables |
| 121 | * specific microarchitectural clock gating |
| 122 | * behaviour. |
| 123 | */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 124 | sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 125 | workaround_reset_end cortex_a510, ERRATUM(2347730) |
Akram Ahmad | a85254e | 2022-07-21 14:01:33 +0100 | [diff] [blame] | 126 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 127 | check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) |
Akram Ahmad | 60accba | 2022-07-22 16:20:44 +0100 | [diff] [blame] | 128 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 129 | workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 |
Akram Ahmad | 60accba | 2022-07-22 16:20:44 +0100 | [diff] [blame] | 130 | /* |
| 131 | * Cacheable atomic operations can be forced |
| 132 | * to be executed near by setting |
| 133 | * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found |
| 134 | * in [40:38] of CPUECTLR_EL1. |
| 135 | */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 136 | sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ |
| 137 | CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 138 | workaround_reset_end cortex_a510, ERRATUM(2371937) |
Akram Ahmad | 60accba | 2022-07-22 16:20:44 +0100 | [diff] [blame] | 139 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 140 | check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) |
Akram Ahmad | 60accba | 2022-07-22 16:20:44 +0100 | [diff] [blame] | 141 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 142 | workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 143 | sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 144 | workaround_reset_end cortex_a510, ERRATUM(2666669) |
Akram Ahmad | 89034d6 | 2022-09-21 13:59:56 +0100 | [diff] [blame] | 145 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 146 | check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) |
Akram Ahmad | 89034d6 | 2022-09-21 13:59:56 +0100 | [diff] [blame] | 147 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 148 | .global erratum_cortex_a510_2684597_wa |
| 149 | workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR |
Andre Przywara | 744043c | 2023-03-23 11:50:32 +0000 | [diff] [blame] | 150 | /* |
| 151 | * Many assemblers do not yet understand the "tsb csync" mnemonic, |
| 152 | * so use the equivalent hint instruction. |
| 153 | */ |
| 154 | hint #18 /* tsb csync */ |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 155 | workaround_runtime_end cortex_a510, ERRATUM(2684597) |
| 156 | |
| 157 | check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) |
| 158 | |
| 159 | /* |
| 160 | * ERRATA_DSU_2313941 : |
| 161 | * The errata is defined in dsu_helpers.S but applies to cortex_a510 |
| 162 | * as well. Henceforth creating symbolic names to the already existing errata |
| 163 | * workaround functions to get them registered under the Errata Framework. |
Harrison Mutai | e5249fe | 2022-12-09 12:14:25 +0000 | [diff] [blame] | 164 | */ |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 165 | .equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941 |
| 166 | .equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa |
| 167 | add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET |
Harrison Mutai | e5249fe | 2022-12-09 12:14:25 +0000 | [diff] [blame] | 168 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 169 | /* ---------------------------------------------------- |
| 170 | * HW will do the cache maintenance while powering down |
| 171 | * ---------------------------------------------------- |
| 172 | */ |
| 173 | func cortex_a510_core_pwr_dwn |
| 174 | /* --------------------------------------------------- |
| 175 | * Enable CPU power down bit in power control register |
| 176 | * --------------------------------------------------- |
| 177 | */ |
Jayanth Dodderi Chidanand | 399472c | 2023-04-11 21:58:21 +0100 | [diff] [blame] | 178 | sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 179 | isb |
| 180 | ret |
| 181 | endfunc cortex_a510_core_pwr_dwn |
| 182 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 183 | errata_report_shim cortex_a510 |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 184 | |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 185 | cpu_reset_func_start cortex_a510 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 186 | /* Disable speculative loads */ |
| 187 | msr SSBS, xzr |
Jayanth Dodderi Chidanand | 5818c7a | 2023-04-11 15:15:31 +0100 | [diff] [blame] | 188 | cpu_reset_func_end cortex_a510 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 189 | |
| 190 | /* --------------------------------------------- |
| 191 | * This function provides Cortex-A510 specific |
| 192 | * register information for crash reporting. |
| 193 | * It needs to return with x6 pointing to |
| 194 | * a list of register names in ascii and |
| 195 | * x8 - x15 having values of registers to be |
| 196 | * reported. |
| 197 | * --------------------------------------------- |
| 198 | */ |
| 199 | .section .rodata.cortex_a510_regs, "aS" |
| 200 | cortex_a510_regs: /* The ascii list of register names to be reported */ |
| 201 | .asciz "cpuectlr_el1", "" |
| 202 | |
| 203 | func cortex_a510_cpu_reg_dump |
| 204 | adr x6, cortex_a510_regs |
| 205 | mrs x8, CORTEX_A510_CPUECTLR_EL1 |
| 206 | ret |
| 207 | endfunc cortex_a510_cpu_reg_dump |
| 208 | |
| 209 | declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ |
| 210 | cortex_a510_reset_func, \ |
| 211 | cortex_a510_core_pwr_dwn |