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Achin Guptaa4f50c22014-05-09 12:17:56 +01001/*
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Guptaa4f50c22014-05-09 12:17:56 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Guptaa4f50c22014-05-09 12:17:56 +01005 */
6
Achin Guptaa4f50c22014-05-09 12:17:56 +01007#include <arch.h>
Achin Guptaa4f50c22014-05-09 12:17:56 +01008#include <asm_macros.S>
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +01009#include <bl_common.h>
10#include <tsp.h>
Achin Guptaa4f50c22014-05-09 12:17:56 +010011
12
13 /* ----------------------------------------------------
14 * The caller-saved registers x0-x18 and LR are saved
15 * here.
16 * ----------------------------------------------------
17 */
18
19#define SCRATCH_REG_SIZE #(20 * 8)
20
21 .macro save_caller_regs_and_lr
22 sub sp, sp, SCRATCH_REG_SIZE
23 stp x0, x1, [sp]
24 stp x2, x3, [sp, #0x10]
25 stp x4, x5, [sp, #0x20]
26 stp x6, x7, [sp, #0x30]
27 stp x8, x9, [sp, #0x40]
28 stp x10, x11, [sp, #0x50]
29 stp x12, x13, [sp, #0x60]
30 stp x14, x15, [sp, #0x70]
31 stp x16, x17, [sp, #0x80]
32 stp x18, x30, [sp, #0x90]
33 .endm
34
35 .macro restore_caller_regs_and_lr
36 ldp x0, x1, [sp]
37 ldp x2, x3, [sp, #0x10]
38 ldp x4, x5, [sp, #0x20]
39 ldp x6, x7, [sp, #0x30]
40 ldp x8, x9, [sp, #0x40]
41 ldp x10, x11, [sp, #0x50]
42 ldp x12, x13, [sp, #0x60]
43 ldp x14, x15, [sp, #0x70]
44 ldp x16, x17, [sp, #0x80]
45 ldp x18, x30, [sp, #0x90]
46 add sp, sp, SCRATCH_REG_SIZE
47 .endm
48
Soby Mathewbec98512015-09-03 18:29:38 +010049 /* ----------------------------------------------------
50 * Common TSP interrupt handling routine
51 * ----------------------------------------------------
52 */
53 .macro handle_tsp_interrupt label
54 /* Enable the SError interrupt */
55 msr daifclr, #DAIF_ABT_BIT
56
57 save_caller_regs_and_lr
58 bl tsp_common_int_handler
59 cbz x0, interrupt_exit_\label
60
61 /*
62 * This interrupt was not targetted to S-EL1 so send it to
63 * the monitor and wait for execution to resume.
64 */
65 smc #0
66interrupt_exit_\label:
67 restore_caller_regs_and_lr
68 eret
69 .endm
70
Achin Guptaa4f50c22014-05-09 12:17:56 +010071 .globl tsp_exceptions
72
73 /* -----------------------------------------------------
74 * TSP exception handlers.
75 * -----------------------------------------------------
76 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010077vector_base tsp_exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +010078 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010079 * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +010080 * are expected and treated as irrecoverable errors.
81 * -----------------------------------------------------
82 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010083vector_entry sync_exception_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000084 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +010085 check_vector_size sync_exception_sp_el0
86
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010087vector_entry irq_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000088 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +010089 check_vector_size irq_sp_el0
90
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010091vector_entry fiq_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000092 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +010093 check_vector_size fiq_sp_el0
94
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010095vector_entry serror_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000096 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +010097 check_vector_size serror_sp_el0
98
99
100 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100101 * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
Achin Guptaa4f50c22014-05-09 12:17:56 +0100102 * are expected and handled
103 * -----------------------------------------------------
104 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100105vector_entry sync_exception_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000106 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100107 check_vector_size sync_exception_sp_elx
108
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100109vector_entry irq_sp_elx
Soby Mathewbec98512015-09-03 18:29:38 +0100110 handle_tsp_interrupt irq_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100111 check_vector_size irq_sp_elx
112
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100113vector_entry fiq_sp_elx
Soby Mathewbec98512015-09-03 18:29:38 +0100114 handle_tsp_interrupt fiq_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100115 check_vector_size fiq_sp_elx
116
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100117vector_entry serror_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000118 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100119 check_vector_size serror_sp_elx
120
121
122 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100123 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100124 * are handled since TSP does not implement a lower EL
125 * -----------------------------------------------------
126 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100127vector_entry sync_exception_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000128 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100129 check_vector_size sync_exception_aarch64
130
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100131vector_entry irq_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000132 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100133 check_vector_size irq_aarch64
134
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100135vector_entry fiq_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000136 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100137 check_vector_size fiq_aarch64
138
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100139vector_entry serror_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000140 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100141 check_vector_size serror_aarch64
142
143
144 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100145 * Lower EL using AArch32 : 0x600 - 0x800. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100146 * handled since the TSP does not implement a lower EL.
147 * -----------------------------------------------------
148 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100149vector_entry sync_exception_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000150 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100151 check_vector_size sync_exception_aarch32
152
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100153vector_entry irq_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000154 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100155 check_vector_size irq_aarch32
156
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100157vector_entry fiq_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000158 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100159 check_vector_size fiq_aarch32
160
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100161vector_entry serror_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000162 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100163 check_vector_size serror_aarch32