blob: 07a46c518d6654da89f7a0b8d1e8d8830b989a80 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +00002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +01006#ifndef PLAT_ARM_H
7#define PLAT_ARM_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Dan Handley9df48042015-03-19 18:58:55 +00009#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <drivers/arm/tzc_common.h>
12#include <lib/bakery_lock.h>
13#include <lib/cassert.h>
14#include <lib/el3_runtime/cpu_data.h>
15#include <lib/spinlock.h>
16#include <lib/utils_def.h>
17#include <lib/xlat_tables/xlat_tables_compat.h>
Dan Handley9df48042015-03-19 18:58:55 +000018
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010019/*******************************************************************************
20 * Forward declarations
21 ******************************************************************************/
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010022struct meminfo;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010023struct image_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +000024struct bl_params;
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010025
Summer Qin5ce394c2018-03-12 11:28:26 +080026typedef struct arm_tzc_regions_info {
27 unsigned long long base;
28 unsigned long long end;
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010029 unsigned int sec_attr;
Summer Qin5ce394c2018-03-12 11:28:26 +080030 unsigned int nsaid_permissions;
31} arm_tzc_regions_info_t;
32
33/*******************************************************************************
34 * Default mapping definition of the TrustZone Controller for ARM standard
35 * platforms.
36 * Configure:
37 * - Region 0 with no access;
38 * - Region 1 with secure access only;
39 * - the remaining DRAM regions access from the given Non-Secure masters.
40 ******************************************************************************/
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +000041#if ENABLE_SPM && SPM_MM
Summer Qin5ce394c2018-03-12 11:28:26 +080042#define ARM_TZC_REGIONS_DEF \
43 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
44 TZC_REGION_S_RDWR, 0}, \
45 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
46 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
47 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
48 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +010049 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
50 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
Summer Qin5ce394c2018-03-12 11:28:26 +080051 PLAT_ARM_TZC_NS_DEV_ACCESS}
52
53#else
54#define ARM_TZC_REGIONS_DEF \
55 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
56 TZC_REGION_S_RDWR, 0}, \
57 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
58 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
59 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
60 PLAT_ARM_TZC_NS_DEV_ACCESS}
61#endif
62
Chris Kay2b54c0c2018-05-09 15:46:07 +010063#define ARM_CASSERT_MMAP \
64 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
65 assert_plat_arm_mmap_mismatch); \
66 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
67 <= MAX_MMAP_REGIONS, \
Dan Handley9df48042015-03-19 18:58:55 +000068 assert_max_mmap_regions);
69
Roberto Vargase3adc372018-05-23 09:27:06 +010070void arm_setup_romlib(void);
71
Julius Werner8e0ef0f2019-07-09 14:02:43 -070072#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
Dan Handley9df48042015-03-19 18:58:55 +000073/*
74 * Use this macro to instantiate lock before it is used in below
75 * arm_lock_xxx() macros
76 */
Sandrine Bailleuxceb258e2018-07-11 13:59:18 +020077#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
Soby Mathewea26bad2016-11-14 12:25:45 +000078#define ARM_LOCK_GET_INSTANCE (&arm_lock)
Roberto Vargas00996942017-11-13 13:41:58 +000079
80#if !HW_ASSISTED_COHERENCY
81#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
82#else
83#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
84#endif
85#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
86
Dan Handley9df48042015-03-19 18:58:55 +000087/*
88 * These are wrapper macros to the Coherent Memory Bakery Lock API.
89 */
90#define arm_lock_init() bakery_lock_init(&arm_lock)
91#define arm_lock_get() bakery_lock_get(&arm_lock)
92#define arm_lock_release() bakery_lock_release(&arm_lock)
93
94#else
95
Dan Handley9df48042015-03-19 18:58:55 +000096/*
Yatharth Kochar2694cba2016-11-14 12:00:41 +000097 * Empty macros for all other BL stages other than BL31 and BL32
Dan Handley9df48042015-03-19 18:58:55 +000098 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010099#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
Soby Mathewea26bad2016-11-14 12:25:45 +0000100#define ARM_LOCK_GET_INSTANCE 0
Dan Handley9df48042015-03-19 18:58:55 +0000101#define arm_lock_init()
102#define arm_lock_get()
103#define arm_lock_release()
104
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700105#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
Dan Handley9df48042015-03-19 18:58:55 +0000106
Soby Mathew7799cf72015-04-16 14:49:09 +0100107#if ARM_RECOM_STATE_ID_ENC
108/*
109 * Macros used to parse state information from State-ID if it is using the
110 * recommended encoding for State-ID.
111 */
112#define ARM_LOCAL_PSTATE_WIDTH 4
113#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
114
115/* Macros to construct the composite power state */
116
117/* Make composite power state parameter till power level 0 */
118#if PSCI_EXTENDED_STATE_ID
119
120#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
121 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
122#else
123#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
124 (((lvl0_state) << PSTATE_ID_SHIFT) | \
125 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
126 ((type) << PSTATE_TYPE_SHIFT))
127#endif /* __PSCI_EXTENDED_STATE_ID__ */
128
129/* Make composite power state parameter till power level 1 */
130#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
131 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
132 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
133
Soby Mathewa869de12015-05-08 10:18:59 +0100134/* Make composite power state parameter till power level 2 */
135#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
136 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
137 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
138
Soby Mathew7799cf72015-04-16 14:49:09 +0100139#endif /* __ARM_RECOM_STATE_ID_ENC__ */
140
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000141/* ARM State switch error codes */
142#define STATE_SW_E_PARAM (-2)
143#define STATE_SW_E_DENIED (-3)
Dan Handley9df48042015-03-19 18:58:55 +0000144
Dan Handley9df48042015-03-19 18:58:55 +0000145/* IO storage utility functions */
146void arm_io_setup(void);
147
148/* Security utility functions */
Summer Qin5ce394c2018-03-12 11:28:26 +0800149void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +0000150struct tzc_dmc500_driver_data;
Summer Qin5ce394c2018-03-12 11:28:26 +0800151void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
152 const arm_tzc_regions_info_t *tzc_regions);
Dan Handley9df48042015-03-19 18:58:55 +0000153
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100154/* Console utility functions */
155void arm_console_boot_init(void);
156void arm_console_boot_end(void);
157void arm_console_runtime_init(void);
158void arm_console_runtime_end(void);
159
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100160/* Systimer utility function */
161void arm_configure_sys_timer(void);
162
Dan Handley9df48042015-03-19 18:58:55 +0000163/* PM utility functions */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100164int arm_validate_power_state(unsigned int power_state,
165 psci_power_state_t *req_state);
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100166int arm_validate_psci_entrypoint(uintptr_t entrypoint);
Soby Mathew0d9e8522015-07-15 13:36:24 +0100167int arm_validate_ns_entrypoint(uintptr_t entrypoint);
Soby Mathew9ca28062017-10-11 16:08:58 +0100168void arm_system_pwr_domain_save(void);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100169void arm_system_pwr_domain_resume(void);
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000170int arm_psci_read_mem_protect(int *enabled);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100171int arm_nor_psci_write_mem_protect(int val);
Roberto Vargas550eb082018-01-05 16:00:05 +0000172void arm_nor_psci_do_static_mem_protect(void);
173void arm_nor_psci_do_dyn_mem_protect(void);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100174int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100175
176/* Topology utility function */
177int arm_check_mpidr(u_register_t mpidr);
Dan Handley9df48042015-03-19 18:58:55 +0000178
179/* BL1 utility functions */
180void arm_bl1_early_platform_setup(void);
181void arm_bl1_platform_setup(void);
182void arm_bl1_plat_arch_setup(void);
183
184/* BL2 utility functions */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000185void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout);
Dan Handley9df48042015-03-19 18:58:55 +0000186void arm_bl2_platform_setup(void);
187void arm_bl2_plat_arch_setup(void);
188uint32_t arm_get_spsr_for_bl32_entry(void);
189uint32_t arm_get_spsr_for_bl33_entry(void);
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000190int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000191int arm_bl2_handle_post_image_load(unsigned int image_id);
Sathees Balya90950092018-11-15 14:22:30 +0000192struct bl_params *arm_get_next_bl_params(void);
Dan Handley9df48042015-03-19 18:58:55 +0000193
Roberto Vargas52207802017-11-17 13:22:18 +0000194/* BL2 at EL3 functions */
195void arm_bl2_el3_early_platform_setup(void);
196void arm_bl2_el3_plat_arch_setup(void);
197
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100198/* BL2U utility functions */
199void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
200 void *plat_info);
201void arm_bl2u_platform_setup(void);
202void arm_bl2u_plat_arch_setup(void);
203
Juan Castillo7d199412015-12-14 09:35:25 +0000204/* BL31 utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000205void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
206 uintptr_t hw_config, void *plat_params_from_bl2);
Dan Handley9df48042015-03-19 18:58:55 +0000207void arm_bl31_platform_setup(void);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000208void arm_bl31_plat_runtime_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000209void arm_bl31_plat_arch_setup(void);
210
211/* TSP utility functions */
212void arm_tsp_early_platform_setup(void);
213
Soby Mathew7b754182016-07-11 14:15:27 +0100214/* SP_MIN utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000215void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
216 uintptr_t hw_config, void *plat_params_from_bl2);
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100217void arm_sp_min_plat_runtime_setup(void);
Soby Mathew7b754182016-07-11 14:15:27 +0100218
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100219/* FIP TOC validity check */
220int arm_io_is_toc_valid(void);
Dan Handley9df48042015-03-19 18:58:55 +0000221
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000222/* Utility functions for Dynamic Config */
223void arm_load_tb_fw_config(void);
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000224void arm_bl2_set_tb_cfg_addr(void *dtb);
225void arm_bl2_dyn_cfg_init(void);
John Tsichritzisc34341a2018-07-30 13:41:52 +0100226void arm_bl1_set_mbedtls_heap(void);
227int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000228
Dan Handley9df48042015-03-19 18:58:55 +0000229/*
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100230 * Free the memory storing initialization code only used during an images boot
231 * time so it can be reclaimed for runtime data
232 */
233void arm_free_init_memory(void);
234
235/*
Dan Handley9df48042015-03-19 18:58:55 +0000236 * Mandatory functions required in ARM standard platforms
237 */
Soby Mathew47e43f22016-02-01 14:04:34 +0000238unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000239void plat_arm_gic_driver_init(void);
Dan Handley9df48042015-03-19 18:58:55 +0000240void plat_arm_gic_init(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000241void plat_arm_gic_cpuif_enable(void);
242void plat_arm_gic_cpuif_disable(void);
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000243void plat_arm_gic_redistif_on(void);
244void plat_arm_gic_redistif_off(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000245void plat_arm_gic_pcpu_init(void);
Soby Mathew9ca28062017-10-11 16:08:58 +0100246void plat_arm_gic_save(void);
247void plat_arm_gic_resume(void);
Dan Handley9df48042015-03-19 18:58:55 +0000248void plat_arm_security_setup(void);
249void plat_arm_pwrc_setup(void);
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000250void plat_arm_interconnect_init(void);
251void plat_arm_interconnect_enter_coherency(void);
252void plat_arm_interconnect_exit_coherency(void);
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100253void plat_arm_program_trusted_mailbox(uintptr_t address);
Sathees Balya22576072018-09-03 17:41:13 +0100254int plat_arm_bl1_fwu_needed(void);
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100255__dead2 void plat_arm_error_handler(int err);
Dan Handley9df48042015-03-19 18:58:55 +0000256
Summer Qin93c812f2017-02-28 16:46:17 +0000257#if ARM_PLAT_MT
258unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
259#endif
260
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100261/*
262 * This function is called after loading SCP_BL2 image and it is used to perform
263 * any platform-specific actions required to handle the SCP firmware.
264 */
265int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100266
Dan Handley9df48042015-03-19 18:58:55 +0000267/*
268 * Optional functions required in ARM standard platforms
269 */
270void plat_arm_io_setup(void);
271int plat_arm_get_alt_image_source(
Juan Castillo3a66aca2015-04-13 17:36:19 +0100272 unsigned int image_id,
273 uintptr_t *dev_handle,
274 uintptr_t *image_spec);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100275unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
Vikram Kanigiri07035432015-11-12 18:52:34 +0000276const mmap_region_t *plat_arm_get_mmap(void);
Dan Handley9df48042015-03-19 18:58:55 +0000277
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100278/* Allow platform to override psci_pm_ops during runtime */
279const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
280
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000281/* Execution state switch in ARM platforms */
282int arm_execution_state_switch(unsigned int smc_fid,
283 uint32_t pc_hi,
284 uint32_t pc_lo,
285 uint32_t cookie_hi,
286 uint32_t cookie_lo,
287 void *handle);
288
Soby Mathew6d07e672018-03-01 10:53:33 +0000289/* Optional functions for SP_MIN */
290void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
291 u_register_t arg2, u_register_t arg3);
292
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000293/* global variables */
294extern plat_psci_ops_t plat_arm_psci_pm_ops;
295extern const mmap_region_t plat_arm_mmap[];
Jeenu Viswambharan4542cfe2018-07-19 08:03:46 +0100296extern const unsigned int arm_pm_idle_states[];
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000297
Aditya Angadi20b48412019-04-16 11:29:14 +0530298/* secure watchdog */
299void plat_arm_secure_wdt_start(void);
300void plat_arm_secure_wdt_stop(void);
301
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +0100302#endif /* PLAT_ARM_H */