Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <string.h> |
| 9 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 10 | #include <arch.h> |
| 11 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 14 | #include <context.h> |
Harvey Hsieh | fbdfce1 | 2016-11-23 19:13:08 +0800 | [diff] [blame] | 15 | #include <cortex_a57.h> |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 16 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <lib/el3_runtime/context_mgmt.h> |
| 18 | #include <lib/psci/psci.h> |
| 19 | #include <plat/common/platform.h> |
| 20 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 21 | #include <mce.h> |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 22 | #include <smmu.h> |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 23 | #include <t18x_ari.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 24 | #include <tegra_private.h> |
| 25 | |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 26 | extern void memcpy16(void *dest, const void *src, unsigned int length); |
| 27 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 28 | extern void prepare_cpu_pwr_dwn(void); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 29 | extern void tegra186_cpu_reset_handler(void); |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 30 | extern uint32_t __tegra186_cpu_reset_handler_end, |
| 31 | __tegra186_smmu_context; |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 32 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 33 | /* state id mask */ |
| 34 | #define TEGRA186_STATE_ID_MASK 0xF |
| 35 | /* constants to get power state's wake time */ |
Krishna Sitaraman | 86569d1 | 2016-08-18 15:41:21 -0700 | [diff] [blame] | 36 | #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 37 | #define TEGRA186_WAKE_TIME_SHIFT 4 |
Varun Wadekar | 698e7c6 | 2016-03-28 15:05:03 -0700 | [diff] [blame] | 38 | /* default core wake mask for CPU_SUSPEND */ |
| 39 | #define TEGRA186_CORE_WAKE_MASK 0x180c |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 40 | /* context size to save during system suspend */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 41 | #define TEGRA186_SE_CONTEXT_SIZE 3 |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 42 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 43 | static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 44 | static struct t18x_psci_percpu_data { |
| 45 | unsigned int wake_time; |
| 46 | } __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 47 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 48 | /* System power down state */ |
| 49 | uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; |
| 50 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 51 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 52 | psci_power_state_t *req_state) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 53 | { |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 54 | int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 55 | int cpu = plat_my_core_pos(); |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 56 | |
Krishna Sitaraman | 86569d1 | 2016-08-18 15:41:21 -0700 | [diff] [blame] | 57 | /* save the core wake time (in TSC ticks)*/ |
| 58 | percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) |
| 59 | << TEGRA186_WAKE_TIME_SHIFT; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 60 | |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 61 | /* |
| 62 | * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that |
| 63 | * the correct value is read in tegra_soc_pwr_domain_suspend(), which |
| 64 | * is called with caches disabled. It is possible to read a stale value |
| 65 | * from DRAM in that function, because the L2 cache is not flushed |
| 66 | * unless the cluster is entering CC6/CC7. |
| 67 | */ |
| 68 | clean_dcache_range((uint64_t)&percpu_data[cpu], |
| 69 | sizeof(percpu_data[cpu])); |
| 70 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 71 | /* Sanity check the requested state id */ |
| 72 | switch (state_id) { |
| 73 | case PSTATE_ID_CORE_IDLE: |
| 74 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 75 | |
| 76 | /* Core powerdown request */ |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 77 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 78 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 79 | |
| 80 | break; |
| 81 | |
| 82 | default: |
| 83 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 84 | return PSCI_E_INVALID_PARAMS; |
| 85 | } |
| 86 | |
| 87 | return PSCI_E_SUCCESS; |
| 88 | } |
| 89 | |
| 90 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
| 91 | { |
| 92 | const plat_local_state_t *pwr_domain_state; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 93 | unsigned int stateid_afflvl0, stateid_afflvl2; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 94 | int cpu = plat_my_core_pos(); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 95 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 96 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 97 | uint64_t smmu_ctx_base; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 98 | uint32_t val; |
| 99 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 100 | /* get the state ID */ |
| 101 | pwr_domain_state = target_state->pwr_domain_state; |
| 102 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
| 103 | TEGRA186_STATE_ID_MASK; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 104 | stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
| 105 | TEGRA186_STATE_ID_MASK; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 106 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 107 | if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || |
| 108 | (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 109 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 110 | /* Enter CPU idle/powerdown */ |
| 111 | val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? |
| 112 | TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; |
| 113 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 114 | percpu_data[cpu].wake_time, 0); |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 115 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 116 | } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 117 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 118 | /* save SE registers */ |
| 119 | se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + |
| 120 | SE_MUTEX_WATCHDOG_NS_LIMIT); |
| 121 | se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + |
| 122 | RNG_MUTEX_WATCHDOG_NS_LIMIT); |
| 123 | se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + |
| 124 | PKA_MUTEX_WATCHDOG_NS_LIMIT); |
| 125 | |
| 126 | /* save 'Secure Boot' Processor Feature Config Register */ |
| 127 | val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); |
| 128 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); |
| 129 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 130 | /* save SMMU context to TZDRAM */ |
| 131 | smmu_ctx_base = params_from_bl2->tzdram_base + |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 132 | ((uintptr_t)&__tegra186_smmu_context - |
| 133 | (uintptr_t)tegra186_cpu_reset_handler); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 134 | tegra_smmu_save_context((uintptr_t)smmu_ctx_base); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 135 | |
| 136 | /* Prepare for system suspend */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 137 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 138 | cstate_info.system = TEGRA_ARI_SYSTEM_SC7; |
| 139 | cstate_info.system_state_force = 1; |
| 140 | cstate_info.update_wake_mask = 1; |
| 141 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 142 | |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 143 | /* Loop until system suspend is allowed */ |
| 144 | do { |
| 145 | val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, |
| 146 | TEGRA_ARI_CORE_C7, |
| 147 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 148 | 0); |
| 149 | } while (val == 0); |
| 150 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 151 | /* Instruct the MCE to enter system suspend state */ |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 152 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 153 | TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | return PSCI_E_SUCCESS; |
| 157 | } |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 158 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 159 | /******************************************************************************* |
| 160 | * Platform handler to calculate the proper target power level at the |
| 161 | * specified affinity level |
| 162 | ******************************************************************************/ |
| 163 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 164 | const plat_local_state_t *states, |
| 165 | unsigned int ncpu) |
| 166 | { |
| 167 | plat_local_state_t target = *states; |
| 168 | int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1; |
| 169 | int core_pos = read_mpidr() & MPIDR_CPU_MASK; |
| 170 | mce_cstate_info_t cstate_info = { 0 }; |
| 171 | |
Varun Wadekar | 4e49a7b | 2017-04-06 17:33:31 -0700 | [diff] [blame] | 172 | /* get the power state at this level */ |
| 173 | if (lvl == MPIDR_AFFLVL1) |
| 174 | target = *(states + core_pos); |
| 175 | if (lvl == MPIDR_AFFLVL2) |
| 176 | target = *(states + cpu); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 177 | |
| 178 | /* CPU suspend */ |
| 179 | if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { |
| 180 | |
| 181 | /* Program default wake mask */ |
| 182 | cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; |
| 183 | cstate_info.update_wake_mask = 1; |
| 184 | mce_update_cstate_info(&cstate_info); |
| 185 | |
| 186 | /* Check if CCx state is allowed. */ |
| 187 | ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 188 | TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, |
| 189 | 0); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 190 | if (ret) |
| 191 | return PSTATE_ID_CORE_POWERDN; |
| 192 | } |
| 193 | |
| 194 | /* CPU off */ |
| 195 | if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { |
| 196 | |
| 197 | /* find out the number of ON cpus in the cluster */ |
| 198 | do { |
| 199 | target = *states++; |
| 200 | if (target != PLAT_MAX_OFF_STATE) |
| 201 | cluster_powerdn = 0; |
| 202 | } while (--ncpu); |
| 203 | |
| 204 | /* Enable cluster powerdn from last CPU in the cluster */ |
| 205 | if (cluster_powerdn) { |
| 206 | |
| 207 | /* Enable CC7 state and turn off wake mask */ |
| 208 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 209 | cstate_info.update_wake_mask = 1; |
| 210 | mce_update_cstate_info(&cstate_info); |
| 211 | |
| 212 | /* Check if CCx state is allowed. */ |
| 213 | ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, |
| 214 | TEGRA_ARI_CORE_C7, |
| 215 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 216 | 0); |
| 217 | if (ret) |
| 218 | return PSTATE_ID_CORE_POWERDN; |
| 219 | |
| 220 | } else { |
| 221 | |
| 222 | /* Turn off wake_mask */ |
| 223 | cstate_info.update_wake_mask = 1; |
| 224 | mce_update_cstate_info(&cstate_info); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | /* System Suspend */ |
Varun Wadekar | 4e49a7b | 2017-04-06 17:33:31 -0700 | [diff] [blame] | 229 | if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && |
| 230 | (target == PSTATE_ID_SOC_POWERDN)) |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 231 | return PSTATE_ID_SOC_POWERDN; |
| 232 | |
| 233 | /* default state */ |
| 234 | return PSCI_LOCAL_STATE_RUN; |
| 235 | } |
| 236 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 237 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 238 | { |
| 239 | const plat_local_state_t *pwr_domain_state = |
| 240 | target_state->pwr_domain_state; |
| 241 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 242 | unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
| 243 | TEGRA186_STATE_ID_MASK; |
Steven Kao | 235e9c3 | 2016-12-23 15:43:17 +0800 | [diff] [blame] | 244 | uint64_t val; |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 245 | |
| 246 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 247 | /* |
| 248 | * The TZRAM loses power when we enter system suspend. To |
| 249 | * allow graceful exit from system suspend, we need to copy |
| 250 | * BL3-1 over to TZDRAM. |
| 251 | */ |
| 252 | val = params_from_bl2->tzdram_base + |
| 253 | ((uintptr_t)&__tegra186_cpu_reset_handler_end - |
| 254 | (uintptr_t)tegra186_cpu_reset_handler); |
| 255 | memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, |
| 256 | (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); |
| 257 | } |
| 258 | |
| 259 | return PSCI_E_SUCCESS; |
| 260 | } |
| 261 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 262 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 263 | { |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 264 | uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; |
| 265 | uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 266 | MPIDR_AFFINITY_BITS; |
| 267 | |
| 268 | if (target_cluster > MPIDR_AFFLVL1) { |
| 269 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); |
| 270 | return PSCI_E_NOT_PRESENT; |
| 271 | } |
| 272 | |
| 273 | /* construct the target CPU # */ |
| 274 | target_cpu |= (target_cluster << 2); |
| 275 | |
| 276 | mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); |
| 277 | |
| 278 | return PSCI_E_SUCCESS; |
| 279 | } |
| 280 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 281 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 282 | { |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 283 | int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
| 284 | int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 285 | mce_cstate_info_t cstate_info = { 0 }; |
Harvey Hsieh | fbdfce1 | 2016-11-23 19:13:08 +0800 | [diff] [blame] | 286 | uint64_t impl, val; |
| 287 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
| 288 | |
| 289 | impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; |
| 290 | |
| 291 | /* |
| 292 | * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186 |
| 293 | * A02p and beyond). |
| 294 | */ |
| 295 | if ((plat_params->l2_ecc_parity_prot_dis != 1) && |
| 296 | (impl != (uint64_t)DENVER_IMPL)) { |
| 297 | |
| 298 | val = read_l2ctlr_el1(); |
| 299 | val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
| 300 | write_l2ctlr_el1(val); |
| 301 | } |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 302 | |
| 303 | /* |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 304 | * Reset power state info for CPUs when onlining, we set |
| 305 | * deepest power when offlining a core but that may not be |
| 306 | * requested by non-secure sw which controls idle states. It |
| 307 | * will re-init this info from non-secure software when the |
| 308 | * core come online. |
Varun Wadekar | d2da47a | 2016-04-09 00:40:45 -0700 | [diff] [blame] | 309 | */ |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 310 | if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { |
| 311 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 312 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; |
| 313 | cstate_info.update_wake_mask = 1; |
| 314 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 315 | } |
Varun Wadekar | d2da47a | 2016-04-09 00:40:45 -0700 | [diff] [blame] | 316 | |
| 317 | /* |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 318 | * Check if we are exiting from deep sleep and restore SE |
| 319 | * context if we are. |
| 320 | */ |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 321 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 322 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 323 | mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, |
| 324 | se_regs[0]); |
| 325 | mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, |
| 326 | se_regs[1]); |
| 327 | mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, |
| 328 | se_regs[2]); |
| 329 | |
| 330 | /* Init SMMU */ |
| 331 | tegra_smmu_init(); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 332 | |
| 333 | /* |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 334 | * Reset power state info for the last core doing SC7 |
| 335 | * entry and exit, we set deepest power state as CC7 |
| 336 | * and SC7 for SC7 entry which may not be requested by |
| 337 | * non-secure SW which controls idle states. |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 338 | */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 339 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 340 | cstate_info.system = TEGRA_ARI_SYSTEM_SC1; |
| 341 | cstate_info.update_wake_mask = 1; |
| 342 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | return PSCI_E_SUCCESS; |
| 346 | } |
| 347 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 348 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 349 | { |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 350 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 351 | |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 352 | /* Disable Denver's DCO operations */ |
| 353 | if (impl == DENVER_IMPL) |
| 354 | denver_disable_dco(); |
| 355 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 356 | /* Turn off CPU */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 357 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 358 | MCE_CORE_SLEEP_TIME_INFINITE, 0); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 359 | |
| 360 | return PSCI_E_SUCCESS; |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 361 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 362 | |
| 363 | __dead2 void tegra_soc_prepare_system_off(void) |
| 364 | { |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 365 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 366 | uint32_t val; |
| 367 | |
| 368 | if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { |
| 369 | |
| 370 | /* power off the entire system */ |
| 371 | mce_enter_ccplex_state(tegra186_system_powerdn_state); |
| 372 | |
| 373 | } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { |
| 374 | |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 375 | /* Prepare for quasi power down */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 376 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 377 | cstate_info.system = TEGRA_ARI_SYSTEM_SC8; |
| 378 | cstate_info.system_state_force = 1; |
| 379 | cstate_info.update_wake_mask = 1; |
| 380 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 381 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 382 | /* loop until other CPUs power down */ |
| 383 | do { |
| 384 | val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, |
| 385 | TEGRA_ARI_CORE_C7, |
| 386 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 387 | 0); |
| 388 | } while (val == 0); |
| 389 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 390 | /* Enter quasi power down state */ |
| 391 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 392 | TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); |
| 393 | |
| 394 | /* disable GICC */ |
| 395 | tegra_gic_cpuif_deactivate(); |
| 396 | |
| 397 | /* power down core */ |
| 398 | prepare_cpu_pwr_dwn(); |
| 399 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 400 | /* flush L1/L2 data caches */ |
| 401 | dcsw_op_all(DCCISW); |
| 402 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 403 | } else { |
| 404 | ERROR("%s: unsupported power down state (%d)\n", __func__, |
| 405 | tegra186_system_powerdn_state); |
| 406 | } |
| 407 | |
| 408 | wfi(); |
| 409 | |
| 410 | /* wait for the system to power down */ |
| 411 | for (;;) { |
| 412 | ; |
| 413 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 414 | } |
Varun Wadekar | 38020c9 | 2016-01-07 14:36:12 -0800 | [diff] [blame] | 415 | |
| 416 | int tegra_soc_prepare_system_reset(void) |
| 417 | { |
| 418 | mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); |
| 419 | |
| 420 | return PSCI_E_SUCCESS; |
| 421 | } |