Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 32 | #include <asm_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <context.h> |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 34 | #include <cpu_data.h> |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 35 | #include <interrupt_mgmt.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 36 | #include <platform_def.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <runtime_svc.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | |
| 39 | .globl runtime_exceptions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 41 | /* --------------------------------------------------------------------- |
| 42 | * This macro handles Synchronous exceptions. |
| 43 | * Only SMC exceptions are supported. |
| 44 | * --------------------------------------------------------------------- |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 45 | */ |
| 46 | .macro handle_sync_exception |
Achin Gupta | ed1744e | 2014-08-04 23:13:10 +0100 | [diff] [blame] | 47 | /* Enable the SError interrupt */ |
| 48 | msr daifclr, #DAIF_ABT_BIT |
| 49 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 50 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 51 | |
| 52 | #if ENABLE_RUNTIME_INSTRUMENTATION |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 53 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 54 | * Read the timestamp value and store it in per-cpu data. The value |
| 55 | * will be extracted from per-cpu data by the C level SMC handler and |
| 56 | * saved to the PMF timestamp region. |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 57 | */ |
| 58 | mrs x30, cntpct_el0 |
| 59 | str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 60 | mrs x29, tpidr_el3 |
| 61 | str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] |
| 62 | ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 63 | #endif |
| 64 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 65 | mrs x30, esr_el3 |
| 66 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 67 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 68 | /* Handle SMC exceptions separately from other synchronous exceptions */ |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 69 | cmp x30, #EC_AARCH32_SMC |
| 70 | b.eq smc_handler32 |
| 71 | |
| 72 | cmp x30, #EC_AARCH64_SMC |
| 73 | b.eq smc_handler64 |
| 74 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 75 | /* Other kinds of synchronous exceptions are not handled */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 76 | bl report_unhandled_exception |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 77 | .endm |
| 78 | |
| 79 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 80 | /* --------------------------------------------------------------------- |
| 81 | * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS |
| 82 | * interrupts. |
| 83 | * --------------------------------------------------------------------- |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 84 | */ |
| 85 | .macro handle_interrupt_exception label |
Achin Gupta | ed1744e | 2014-08-04 23:13:10 +0100 | [diff] [blame] | 86 | /* Enable the SError interrupt */ |
| 87 | msr daifclr, #DAIF_ABT_BIT |
| 88 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 89 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 90 | bl save_gp_registers |
| 91 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 92 | /* Save the EL3 system registers needed to return from this exception */ |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 93 | mrs x0, spsr_el3 |
| 94 | mrs x1, elr_el3 |
| 95 | stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 96 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 97 | /* Switch to the runtime stack i.e. SP_EL0 */ |
| 98 | ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 99 | mov x20, sp |
| 100 | msr spsel, #0 |
| 101 | mov sp, x2 |
| 102 | |
| 103 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 104 | * Find out whether this is a valid interrupt type. |
| 105 | * If the interrupt controller reports a spurious interrupt then return |
| 106 | * to where we came from. |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 107 | */ |
Dan Handley | 701fea7 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 108 | bl plat_ic_get_pending_interrupt_type |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 109 | cmp x0, #INTR_TYPE_INVAL |
| 110 | b.eq interrupt_exit_\label |
| 111 | |
| 112 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 113 | * Get the registered handler for this interrupt type. |
| 114 | * A NULL return value could be 'cause of the following conditions: |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 115 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 116 | * a. An interrupt of a type was routed correctly but a handler for its |
| 117 | * type was not registered. |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 118 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 119 | * b. An interrupt of a type was not routed correctly so a handler for |
| 120 | * its type was not registered. |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 121 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 122 | * c. An interrupt of a type was routed correctly to EL3, but was |
| 123 | * deasserted before its pending state could be read. Another |
| 124 | * interrupt of a different type pended at the same time and its |
| 125 | * type was reported as pending instead. However, a handler for this |
| 126 | * type was not registered. |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 127 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 128 | * a. and b. can only happen due to a programming error. The |
| 129 | * occurrence of c. could be beyond the control of Trusted Firmware. |
| 130 | * It makes sense to return from this exception instead of reporting an |
| 131 | * error. |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 132 | */ |
| 133 | bl get_interrupt_type_handler |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 134 | cbz x0, interrupt_exit_\label |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 135 | mov x21, x0 |
| 136 | |
| 137 | mov x0, #INTR_ID_UNAVAILABLE |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 138 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 139 | /* Set the current security state in the 'flags' parameter */ |
| 140 | mrs x2, scr_el3 |
| 141 | ubfx x1, x2, #0, #1 |
| 142 | |
| 143 | /* Restore the reference to the 'handle' i.e. SP_EL3 */ |
| 144 | mov x2, x20 |
| 145 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 146 | /* x3 will point to a cookie (not used now) */ |
Soby Mathew | 799f0ab | 2014-05-27 16:54:31 +0100 | [diff] [blame] | 147 | mov x3, xzr |
| 148 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 149 | /* Call the interrupt type handler */ |
| 150 | blr x21 |
| 151 | |
| 152 | interrupt_exit_\label: |
| 153 | /* Return from exception, possibly in a different security state */ |
| 154 | b el3_exit |
| 155 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 156 | .endm |
| 157 | |
| 158 | |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 159 | .macro save_x18_to_x29_sp_el0 |
| 160 | stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] |
| 161 | stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] |
| 162 | stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] |
| 163 | stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] |
| 164 | stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] |
| 165 | stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
| 166 | mrs x18, sp_el0 |
| 167 | str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] |
| 168 | .endm |
| 169 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 170 | |
| 171 | vector_base runtime_exceptions |
| 172 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 173 | /* --------------------------------------------------------------------- |
| 174 | * Current EL with SP_EL0 : 0x0 - 0x200 |
| 175 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 176 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 177 | vector_entry sync_exception_sp_el0 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 178 | /* We don't expect any synchronous exceptions from EL3 */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 179 | bl report_unhandled_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 180 | check_vector_size sync_exception_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 181 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 182 | vector_entry irq_sp_el0 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 183 | /* |
| 184 | * EL3 code is non-reentrant. Any asynchronous exception is a serious |
| 185 | * error. Loop infinitely. |
| 186 | */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 187 | bl report_unhandled_interrupt |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 188 | check_vector_size irq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 189 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 190 | |
| 191 | vector_entry fiq_sp_el0 |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 192 | bl report_unhandled_interrupt |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 193 | check_vector_size fiq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 194 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 195 | |
| 196 | vector_entry serror_sp_el0 |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 197 | bl report_unhandled_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 198 | check_vector_size serror_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 199 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 200 | /* --------------------------------------------------------------------- |
| 201 | * Current EL with SP_ELx: 0x200 - 0x400 |
| 202 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 204 | vector_entry sync_exception_sp_elx |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 205 | /* |
| 206 | * This exception will trigger if anything went wrong during a previous |
| 207 | * exception entry or exit or while handling an earlier unexpected |
| 208 | * synchronous exception. There is a high probability that SP_EL3 is |
| 209 | * corrupted. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 210 | */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 211 | bl report_unhandled_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 212 | check_vector_size sync_exception_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 213 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 214 | vector_entry irq_sp_elx |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 215 | bl report_unhandled_interrupt |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 216 | check_vector_size irq_sp_elx |
| 217 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 218 | vector_entry fiq_sp_elx |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 219 | bl report_unhandled_interrupt |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 220 | check_vector_size fiq_sp_elx |
| 221 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 222 | vector_entry serror_sp_elx |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 223 | bl report_unhandled_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 224 | check_vector_size serror_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 225 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 226 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 227 | * Lower EL using AArch64 : 0x400 - 0x600 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 228 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 229 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 230 | vector_entry sync_exception_aarch64 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 231 | /* |
| 232 | * This exception vector will be the entry point for SMCs and traps |
| 233 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 234 | * to a valid cpu context where the general purpose and system register |
| 235 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 236 | */ |
| 237 | handle_sync_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 238 | check_vector_size sync_exception_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 239 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 240 | vector_entry irq_aarch64 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 241 | handle_interrupt_exception irq_aarch64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 242 | check_vector_size irq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 243 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 244 | vector_entry fiq_aarch64 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 245 | handle_interrupt_exception fiq_aarch64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 246 | check_vector_size fiq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 247 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 248 | vector_entry serror_aarch64 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 249 | /* |
| 250 | * SError exceptions from lower ELs are not currently supported. |
| 251 | * Report their occurrence. |
| 252 | */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 253 | bl report_unhandled_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 254 | check_vector_size serror_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 255 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 256 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 257 | * Lower EL using AArch32 : 0x600 - 0x800 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 258 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 259 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 260 | vector_entry sync_exception_aarch32 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 261 | /* |
| 262 | * This exception vector will be the entry point for SMCs and traps |
| 263 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 264 | * to a valid cpu context where the general purpose and system register |
| 265 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 266 | */ |
| 267 | handle_sync_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 268 | check_vector_size sync_exception_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 269 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 270 | vector_entry irq_aarch32 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 271 | handle_interrupt_exception irq_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 272 | check_vector_size irq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 273 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 274 | vector_entry fiq_aarch32 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 275 | handle_interrupt_exception fiq_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 276 | check_vector_size fiq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 277 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 278 | vector_entry serror_aarch32 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 279 | /* |
| 280 | * SError exceptions from lower ELs are not currently supported. |
| 281 | * Report their occurrence. |
| 282 | */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 283 | bl report_unhandled_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 284 | check_vector_size serror_aarch32 |
| 285 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 286 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 287 | /* --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 288 | * The following code handles secure monitor calls. |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 289 | * Depending upon the execution state from where the SMC has been |
| 290 | * invoked, it frees some general purpose registers to perform the |
| 291 | * remaining tasks. They involve finding the runtime service handler |
| 292 | * that is the target of the SMC & switching to runtime stacks (SP_EL0) |
| 293 | * before calling the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 294 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 295 | * Note that x30 has been explicitly saved and can be used here |
| 296 | * --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 297 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 298 | func smc_handler |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 299 | smc_handler32: |
| 300 | /* Check whether aarch32 issued an SMC64 */ |
| 301 | tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited |
| 302 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 303 | /* |
| 304 | * Since we're are coming from aarch32, x8-x18 need to be saved as per |
| 305 | * SMC32 calling convention. If a lower EL in aarch64 is making an |
| 306 | * SMC32 call then it must have saved x8-x17 already therein. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 307 | */ |
| 308 | stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] |
| 309 | stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] |
| 310 | stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] |
| 311 | stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] |
| 312 | stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] |
| 313 | |
| 314 | /* x4-x7, x18, sp_el0 are saved below */ |
| 315 | |
| 316 | smc_handler64: |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 317 | /* |
| 318 | * Populate the parameters for the SMC handler. |
| 319 | * We already have x0-x4 in place. x5 will point to a cookie (not used |
| 320 | * now). x6 will point to the context structure (SP_EL3) and x7 will |
| 321 | * contain flags we need to pass to the handler Hence save x5-x7. |
| 322 | * |
| 323 | * Note: x4 only needs to be preserved for AArch32 callers but we do it |
| 324 | * for AArch64 callers as well for convenience |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 325 | */ |
| 326 | stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 327 | stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] |
| 328 | |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 329 | /* Save rest of the gpregs and sp_el0*/ |
| 330 | save_x18_to_x29_sp_el0 |
| 331 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 332 | mov x5, xzr |
| 333 | mov x6, sp |
| 334 | |
| 335 | /* Get the unique owning entity number */ |
| 336 | ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH |
| 337 | ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH |
| 338 | orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH |
| 339 | |
| 340 | adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) |
| 341 | |
| 342 | /* Load descriptor index from array of indices */ |
| 343 | adr x14, rt_svc_descs_indices |
| 344 | ldrb w15, [x14, x16] |
| 345 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 346 | /* |
| 347 | * Restore the saved C runtime stack value which will become the new |
| 348 | * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' |
| 349 | * structure prior to the last ERET from EL3. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 350 | */ |
| 351 | ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 352 | |
| 353 | /* |
| 354 | * Any index greater than 127 is invalid. Check bit 7 for |
| 355 | * a valid index |
| 356 | */ |
| 357 | tbnz w15, 7, smc_unknown |
| 358 | |
| 359 | /* Switch to SP_EL0 */ |
| 360 | msr spsel, #0 |
| 361 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 362 | /* |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 363 | * Get the descriptor using the index |
| 364 | * x11 = (base + off), x15 = index |
| 365 | * |
| 366 | * handler = (base + off) + (index << log2(size)) |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 367 | */ |
| 368 | lsl w10, w15, #RT_SVC_SIZE_LOG2 |
| 369 | ldr x15, [x11, w10, uxtw] |
| 370 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 371 | /* |
| 372 | * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world |
| 373 | * switch during SMC handling. |
| 374 | * TODO: Revisit if all system registers can be saved later. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 375 | */ |
| 376 | mrs x16, spsr_el3 |
| 377 | mrs x17, elr_el3 |
| 378 | mrs x18, scr_el3 |
| 379 | stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 380 | str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 381 | |
| 382 | /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ |
| 383 | bfi x7, x18, #0, #1 |
| 384 | |
| 385 | mov sp, x12 |
| 386 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 387 | /* |
| 388 | * Call the Secure Monitor Call handler and then drop directly into |
| 389 | * el3_exit() which will program any remaining architectural state |
| 390 | * prior to issuing the ERET to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 391 | */ |
| 392 | #if DEBUG |
| 393 | cbz x15, rt_svc_fw_critical_error |
| 394 | #endif |
| 395 | blr x15 |
| 396 | |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 397 | b el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 398 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 399 | smc_unknown: |
| 400 | /* |
| 401 | * Here we restore x4-x18 regardless of where we came from. AArch32 |
| 402 | * callers will find the registers contents unchanged, but AArch64 |
| 403 | * callers will find the registers modified (with stale earlier NS |
| 404 | * content). Either way, we aren't leaking any secure information |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 405 | * through them. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 406 | */ |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 407 | mov w0, #SMC_UNK |
| 408 | b restore_gp_registers_callee_eret |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 409 | |
| 410 | smc_prohibited: |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 411 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 412 | mov w0, #SMC_UNK |
| 413 | eret |
| 414 | |
| 415 | rt_svc_fw_critical_error: |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 416 | /* Switch to SP_ELx */ |
| 417 | msr spsel, #1 |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 418 | bl report_unhandled_exception |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 419 | endfunc smc_handler |