Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 32 | #include <arm_config.h> |
Dan Handley | fb42b12 | 2014-06-20 09:43:15 +0100 | [diff] [blame] | 33 | #include <arm_gic.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 34 | #include <assert.h> |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 35 | #include <debug.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 36 | #include <errno.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <mmio.h> |
| 38 | #include <platform.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 39 | #include <plat_arm.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | #include <psci.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 41 | #include <v2m_def.h> |
Dan Handley | 4d2e49d | 2014-04-11 11:52:12 +0100 | [diff] [blame] | 42 | #include "drivers/pwrc/fvp_pwrc.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 43 | #include "fvp_def.h" |
| 44 | #include "fvp_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 45 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 46 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 47 | #if ARM_RECOM_STATE_ID_ENC |
| 48 | /* |
| 49 | * The table storing the valid idle power states. Ensure that the |
| 50 | * array entries are populated in ascending order of state-id to |
| 51 | * enable us to use binary search during power state validation. |
| 52 | * The table must be terminated by a NULL entry. |
| 53 | */ |
| 54 | const unsigned int arm_pm_idle_states[] = { |
| 55 | /* State-id - 0x01 */ |
| 56 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, |
| 57 | ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), |
| 58 | /* State-id - 0x02 */ |
| 59 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, |
| 60 | ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), |
| 61 | /* State-id - 0x22 */ |
| 62 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, |
| 63 | ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), |
| 64 | 0, |
| 65 | }; |
| 66 | #endif |
| 67 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 68 | /******************************************************************************* |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 69 | * Function which implements the common FVP specific operations to power down a |
| 70 | * cpu in response to a CPU_OFF or CPU_SUSPEND request. |
| 71 | ******************************************************************************/ |
Sandrine Bailleux | a64a854 | 2015-03-05 10:54:34 +0000 | [diff] [blame] | 72 | static void fvp_cpu_pwrdwn_common(void) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 73 | { |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 74 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 75 | arm_gic_cpuif_deactivate(); |
| 76 | |
| 77 | /* Program the power controller to power off this cpu. */ |
| 78 | fvp_pwrc_write_ppoffr(read_mpidr_el1()); |
| 79 | } |
| 80 | |
| 81 | /******************************************************************************* |
| 82 | * Function which implements the common FVP specific operations to power down a |
| 83 | * cluster in response to a CPU_OFF or CPU_SUSPEND request. |
| 84 | ******************************************************************************/ |
Sandrine Bailleux | a64a854 | 2015-03-05 10:54:34 +0000 | [diff] [blame] | 85 | static void fvp_cluster_pwrdwn_common(void) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 86 | { |
| 87 | uint64_t mpidr = read_mpidr_el1(); |
| 88 | |
| 89 | /* Disable coherency if this cluster is to be turned off */ |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 90 | fvp_cci_disable(); |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 91 | |
| 92 | /* Program the power controller to turn the cluster off */ |
| 93 | fvp_pwrc_write_pcoffr(mpidr); |
| 94 | } |
| 95 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame^] | 96 | static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) |
| 97 | { |
| 98 | unsigned long mpidr; |
| 99 | |
| 100 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 101 | ARM_LOCAL_STATE_OFF); |
| 102 | |
| 103 | /* Get the mpidr for this cpu */ |
| 104 | mpidr = read_mpidr_el1(); |
| 105 | |
| 106 | /* Perform the common cluster specific operations */ |
| 107 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 108 | ARM_LOCAL_STATE_OFF) { |
| 109 | /* |
| 110 | * This CPU might have woken up whilst the cluster was |
| 111 | * attempting to power down. In this case the FVP power |
| 112 | * controller will have a pending cluster power off request |
| 113 | * which needs to be cleared by writing to the PPONR register. |
| 114 | * This prevents the power controller from interpreting a |
| 115 | * subsequent entry of this cpu into a simple wfi as a power |
| 116 | * down request. |
| 117 | */ |
| 118 | fvp_pwrc_write_pponr(mpidr); |
| 119 | |
| 120 | /* Enable coherency if this cluster was off */ |
| 121 | fvp_cci_enable(); |
| 122 | } |
| 123 | |
| 124 | /* |
| 125 | * Clear PWKUPR.WEN bit to ensure interrupts do not interfere |
| 126 | * with a cpu power down unless the bit is set again |
| 127 | */ |
| 128 | fvp_pwrc_clr_wen(mpidr); |
| 129 | } |
| 130 | |
| 131 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 132 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 133 | * FVP handler called when a CPU is about to enter standby. |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 134 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 135 | void fvp_cpu_standby(plat_local_state_t cpu_state) |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 136 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 137 | |
| 138 | assert(cpu_state == ARM_LOCAL_STATE_RET); |
| 139 | |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 140 | /* |
| 141 | * Enter standby state |
| 142 | * dsb is good practice before using wfi to enter low power states |
| 143 | */ |
| 144 | dsb(); |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 145 | wfi(); |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 149 | * FVP handler called when a power domain is about to be turned on. The |
| 150 | * mpidr determines the CPU to be turned on. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 151 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 152 | int fvp_pwr_domain_on(u_register_t mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 153 | { |
| 154 | int rc = PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 155 | unsigned int psysr; |
| 156 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 157 | /* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 158 | * Ensure that we do not cancel an inflight power off request |
| 159 | * for the target cpu. That would leave it in a zombie wfi. |
| 160 | * Wait for it to power off, program the jump address for the |
| 161 | * target cpu and then program the power controller to turn |
| 162 | * that cpu on |
| 163 | */ |
| 164 | do { |
| 165 | psysr = fvp_pwrc_read_psysr(mpidr); |
| 166 | } while (psysr & PSYSR_AFF_L0); |
| 167 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 168 | fvp_pwrc_write_pponr(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | return rc; |
| 170 | } |
| 171 | |
| 172 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 173 | * FVP handler called when a power domain is about to be turned off. The |
| 174 | * target_state encodes the power state that each level should transition to. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 175 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 176 | void fvp_pwr_domain_off(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 178 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 179 | ARM_LOCAL_STATE_OFF); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 180 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 181 | /* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 182 | * If execution reaches this stage then this power domain will be |
| 183 | * suspended. Perform at least the cpu specific actions followed |
| 184 | * by the cluster specific operations if applicable. |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 185 | */ |
| 186 | fvp_cpu_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 187 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 188 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 189 | ARM_LOCAL_STATE_OFF) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 190 | fvp_cluster_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 191 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 195 | * FVP handler called when a power domain is about to be suspended. The |
| 196 | * target_state encodes the power state that each level should transition to. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 197 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 198 | void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 199 | { |
Soby Mathew | ffb4ab1 | 2014-09-26 15:08:52 +0100 | [diff] [blame] | 200 | unsigned long mpidr; |
| 201 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 202 | /* |
| 203 | * FVP has retention only at cpu level. Just return |
| 204 | * as nothing is to be done for retention. |
| 205 | */ |
| 206 | if (target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 207 | ARM_LOCAL_STATE_RET) |
Soby Mathew | 74e52a7 | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 208 | return; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 209 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 210 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 211 | ARM_LOCAL_STATE_OFF); |
| 212 | |
Soby Mathew | ffb4ab1 | 2014-09-26 15:08:52 +0100 | [diff] [blame] | 213 | /* Get the mpidr for this cpu */ |
| 214 | mpidr = read_mpidr_el1(); |
| 215 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 216 | /* Program the power controller to enable wakeup interrupts. */ |
| 217 | fvp_pwrc_set_wen(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 218 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 219 | /* Perform the common cpu specific operations */ |
| 220 | fvp_cpu_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 221 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 222 | /* Perform the common cluster specific operations */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 223 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 224 | ARM_LOCAL_STATE_OFF) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 225 | fvp_cluster_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 229 | * FVP handler called when a power domain has just been powered on after |
| 230 | * being turned off earlier. The target_state encodes the low power state that |
| 231 | * each level has woken up from. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 232 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 233 | void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 234 | { |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame^] | 235 | fvp_power_domain_on_finish_common(target_state); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 236 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 237 | /* Enable the gic cpu interface */ |
| 238 | arm_gic_cpuif_setup(); |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame^] | 239 | /* Program the gic per-cpu distributor interface */ |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 240 | arm_gic_pcpu_distif_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 244 | * FVP handler called when a power domain has just been powered on after |
| 245 | * having been suspended earlier. The target_state encodes the low power state |
| 246 | * that each level has woken up from. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 247 | * TODO: At the moment we reuse the on finisher and reinitialize the secure |
| 248 | * context. Need to implement a separate suspend finisher. |
| 249 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 250 | void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 251 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 252 | /* |
| 253 | * Nothing to be done on waking up from retention from CPU level. |
| 254 | */ |
| 255 | if (target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 256 | ARM_LOCAL_STATE_RET) |
| 257 | return; |
| 258 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame^] | 259 | fvp_power_domain_on_finish_common(target_state); |
| 260 | |
| 261 | /* Enable the gic cpu interface */ |
| 262 | arm_gic_cpuif_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 263 | } |
| 264 | |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 265 | /******************************************************************************* |
| 266 | * FVP handlers to shutdown/reboot the system |
| 267 | ******************************************************************************/ |
| 268 | static void __dead2 fvp_system_off(void) |
| 269 | { |
| 270 | /* Write the System Configuration Control Register */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 271 | mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 272 | V2M_CFGCTRL_START | |
| 273 | V2M_CFGCTRL_RW | |
| 274 | V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 275 | wfi(); |
| 276 | ERROR("FVP System Off: operation not handled.\n"); |
| 277 | panic(); |
| 278 | } |
| 279 | |
| 280 | static void __dead2 fvp_system_reset(void) |
| 281 | { |
| 282 | /* Write the System Configuration Control Register */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 283 | mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 284 | V2M_CFGCTRL_START | |
| 285 | V2M_CFGCTRL_RW | |
| 286 | V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 287 | wfi(); |
| 288 | ERROR("FVP System Reset: operation not handled.\n"); |
| 289 | panic(); |
| 290 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 291 | |
| 292 | /******************************************************************************* |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 293 | * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard |
| 294 | * platform layer will take care of registering the handlers with PSCI. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 295 | ******************************************************************************/ |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 296 | const plat_psci_ops_t plat_arm_psci_pm_ops = { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 297 | .cpu_standby = fvp_cpu_standby, |
| 298 | .pwr_domain_on = fvp_pwr_domain_on, |
| 299 | .pwr_domain_off = fvp_pwr_domain_off, |
| 300 | .pwr_domain_suspend = fvp_pwr_domain_suspend, |
| 301 | .pwr_domain_on_finish = fvp_pwr_domain_on_finish, |
| 302 | .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 303 | .system_off = fvp_system_off, |
Soby Mathew | 74e52a7 | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 304 | .system_reset = fvp_system_reset, |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 305 | .validate_power_state = arm_validate_power_state, |
| 306 | .validate_ns_entrypoint = arm_validate_ns_entrypoint |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 307 | }; |