| Jit Loon Lim | a7f5494 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | #include <stdbool.h> |
| 10 | #include <string.h> |
| 11 | |
| 12 | #include <arch_helpers.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <drivers/cadence/cdns_nand.h> |
| 15 | #include <drivers/delay_timer.h> |
| 16 | #include <lib/mmio.h> |
| 17 | #include <lib/utils.h> |
| 18 | #include "nand.h" |
| 19 | |
| 20 | #include "agilex5_pinmux.h" |
| 21 | #include "combophy/combophy.h" |
| 22 | |
| 23 | /* Pinmux configuration */ |
| 24 | static void nand_pinmux_config(void) |
| 25 | { |
| 26 | mmio_write_32(SOCFPGA_PINMUX(PIN0SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 27 | mmio_write_32(SOCFPGA_PINMUX(PIN1SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 28 | mmio_write_32(SOCFPGA_PINMUX(PIN2SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 29 | mmio_write_32(SOCFPGA_PINMUX(PIN3SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 30 | mmio_write_32(SOCFPGA_PINMUX(PIN4SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 31 | mmio_write_32(SOCFPGA_PINMUX(PIN5SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 32 | mmio_write_32(SOCFPGA_PINMUX(PIN6SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 33 | mmio_write_32(SOCFPGA_PINMUX(PIN7SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 34 | mmio_write_32(SOCFPGA_PINMUX(PIN8SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 35 | mmio_write_32(SOCFPGA_PINMUX(PIN9SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 36 | mmio_write_32(SOCFPGA_PINMUX(PIN10SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 37 | mmio_write_32(SOCFPGA_PINMUX(PIN11SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 38 | mmio_write_32(SOCFPGA_PINMUX(PIN12SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 39 | mmio_write_32(SOCFPGA_PINMUX(PIN13SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 40 | mmio_write_32(SOCFPGA_PINMUX(PIN14SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 41 | mmio_write_32(SOCFPGA_PINMUX(PIN16SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 42 | mmio_write_32(SOCFPGA_PINMUX(PIN17SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 43 | mmio_write_32(SOCFPGA_PINMUX(PIN18SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 44 | mmio_write_32(SOCFPGA_PINMUX(PIN19SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 45 | mmio_write_32(SOCFPGA_PINMUX(PIN20SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 46 | mmio_write_32(SOCFPGA_PINMUX(PIN21SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 47 | mmio_write_32(SOCFPGA_PINMUX(PIN22SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 48 | mmio_write_32(SOCFPGA_PINMUX(PIN23SEL), SOCFPGA_PINMUX_SEL_NAND); |
| 49 | } |
| 50 | |
| 51 | int nand_init(handoff *hoff_ptr) |
| 52 | { |
| 53 | /* NAND pin mux configuration */ |
| 54 | nand_pinmux_config(); |
| 55 | |
| 56 | return cdns_nand_host_init(); |
| 57 | } |