Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Samarth Parikh | 59cfa13 | 2017-11-23 14:23:21 +0530 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <lib/bakery_lock.h> |
| 13 | #include <lib/mmio.h> |
| 14 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 15 | #include <plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | #include "css_mhu.h" |
| 18 | |
| 19 | /* SCP MHU secure channel registers */ |
| 20 | #define SCP_INTR_S_STAT 0x200 |
| 21 | #define SCP_INTR_S_SET 0x208 |
| 22 | #define SCP_INTR_S_CLEAR 0x210 |
| 23 | |
| 24 | /* CPU MHU secure channel registers */ |
| 25 | #define CPU_INTR_S_STAT 0x300 |
| 26 | #define CPU_INTR_S_SET 0x308 |
| 27 | #define CPU_INTR_S_CLEAR 0x310 |
| 28 | |
Jeenu Viswambharan | 749d25b | 2017-08-23 14:12:59 +0100 | [diff] [blame] | 29 | ARM_INSTANTIATE_LOCK; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 30 | |
| 31 | /* Weak definition may be overridden in specific CSS based platform */ |
| 32 | #pragma weak plat_arm_pwrc_setup |
| 33 | |
| 34 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 35 | /* |
| 36 | * Slot 31 is reserved because the MHU hardware uses this register bit to |
| 37 | * indicate a non-secure access attempt. The total number of available slots is |
| 38 | * therefore 31 [30:0]. |
| 39 | */ |
| 40 | #define MHU_MAX_SLOT_ID 30 |
| 41 | |
| 42 | void mhu_secure_message_start(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 43 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 44 | assert(slot_id <= MHU_MAX_SLOT_ID); |
| 45 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 46 | arm_lock_get(); |
| 47 | |
| 48 | /* Make sure any previous command has finished */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 49 | while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & |
| 50 | (1 << slot_id)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 51 | ; |
| 52 | } |
| 53 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 54 | void mhu_secure_message_send(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 55 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 56 | assert(slot_id <= MHU_MAX_SLOT_ID); |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 57 | assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & |
| 58 | (1 << slot_id))); |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 59 | |
| 60 | /* Send command to SCP */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 61 | mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | uint32_t mhu_secure_message_wait(void) |
| 65 | { |
| 66 | /* Wait for response from SCP */ |
| 67 | uint32_t response; |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 68 | while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 69 | ; |
| 70 | |
| 71 | return response; |
| 72 | } |
| 73 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 74 | void mhu_secure_message_end(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 75 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 76 | assert(slot_id <= MHU_MAX_SLOT_ID); |
| 77 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 78 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 79 | * Clear any response we got by writing one in the relevant slot bit to |
| 80 | * the CLEAR register |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 81 | */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 82 | mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 83 | |
| 84 | arm_lock_release(); |
| 85 | } |
| 86 | |
Daniel Boulby | f45a4bb | 2018-09-18 13:26:03 +0100 | [diff] [blame] | 87 | void __init mhu_secure_init(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 88 | { |
| 89 | arm_lock_init(); |
| 90 | |
| 91 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 92 | * The STAT register resets to zero. Ensure it is in the expected state, |
| 93 | * as a stale or garbage value would make us think it's a message we've |
| 94 | * already sent. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 95 | */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 96 | assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 97 | } |
| 98 | |
Daniel Boulby | f45a4bb | 2018-09-18 13:26:03 +0100 | [diff] [blame] | 99 | void __init plat_arm_pwrc_setup(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 100 | { |
| 101 | mhu_secure_init(); |
| 102 | } |