Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 8 | #include <errno.h> |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 9 | #include <lib/el3_runtime/context_mgmt.h> |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 10 | #include "spmd_private.h" |
| 11 | |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 12 | /******************************************************************************* |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 13 | * spmd_build_spmc_message |
| 14 | * |
| 15 | * Builds an SPMD to SPMC direct message request. |
| 16 | ******************************************************************************/ |
| 17 | static void spmd_build_spmc_message(gp_regs_t *gpregs, unsigned long long message) |
| 18 | { |
| 19 | write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); |
| 20 | write_ctx_reg(gpregs, CTX_GPREG_X1, |
| 21 | (SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) | |
| 22 | spmd_spmc_id_get()); |
| 23 | write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_PARAM_MBZ); |
| 24 | write_ctx_reg(gpregs, CTX_GPREG_X3, message); |
| 25 | } |
| 26 | |
| 27 | /******************************************************************************* |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 28 | * spmd_pm_secondary_core_set_ep |
| 29 | ******************************************************************************/ |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 30 | int spmd_pm_secondary_core_set_ep(unsigned long long mpidr, |
| 31 | uintptr_t entry_point, unsigned long long context) |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 32 | { |
| 33 | int id = plat_core_pos_by_mpidr(mpidr); |
| 34 | |
Andre Przywara | 05b3370 | 2020-10-02 11:54:56 +0100 | [diff] [blame] | 35 | if ((id < 0) || ((unsigned int)id >= PLATFORM_CORE_COUNT)) { |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 36 | ERROR("%s inconsistent MPIDR (%llx)\n", __func__, mpidr); |
| 37 | return -EINVAL; |
| 38 | } |
| 39 | |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 40 | /* |
| 41 | * Check entry_point address is a PA within |
| 42 | * load_address <= entry_point < load_address + binary_size |
| 43 | */ |
| 44 | if (!spmd_check_address_in_binary_image(entry_point)) { |
| 45 | ERROR("%s entry point is not within image boundaries (%llx)\n", |
| 46 | __func__, mpidr); |
| 47 | return -EINVAL; |
| 48 | } |
| 49 | |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 50 | spmd_spm_core_context_t *ctx = spmd_get_context_by_mpidr(mpidr); |
| 51 | spmd_pm_secondary_ep_t *secondary_ep = &ctx->secondary_ep; |
| 52 | if (secondary_ep->locked) { |
| 53 | ERROR("%s entry locked (%llx)\n", __func__, mpidr); |
| 54 | return -EINVAL; |
| 55 | } |
| 56 | |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 57 | /* Fill new entry to corresponding secondary core id and lock it */ |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 58 | secondary_ep->entry_point = entry_point; |
| 59 | secondary_ep->context = context; |
| 60 | secondary_ep->locked = true; |
Olivier Deprez | 33e4412 | 2020-04-16 17:54:27 +0200 | [diff] [blame] | 61 | |
| 62 | VERBOSE("%s %d %llx %lx %llx\n", |
| 63 | __func__, id, mpidr, entry_point, context); |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 68 | /******************************************************************************* |
| 69 | * This CPU has been turned on. Enter SPMC to initialise S-EL1 or S-EL2. As part |
| 70 | * of the SPMC initialization path, they will initialize any SPs that they |
| 71 | * manage. Entry into SPMC is done after initialising minimal architectural |
| 72 | * state that guarantees safe execution. |
| 73 | ******************************************************************************/ |
| 74 | static void spmd_cpu_on_finish_handler(u_register_t unused) |
| 75 | { |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 76 | entry_point_info_t *spmc_ep_info = spmd_spmc_ep_info_get(); |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 77 | spmd_spm_core_context_t *ctx = spmd_get_context(); |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 78 | unsigned int linear_id = plat_my_core_pos(); |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 79 | uint64_t rc; |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 80 | |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 81 | assert(ctx != NULL); |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 82 | assert(ctx->state != SPMC_STATE_ON); |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 83 | assert(spmc_ep_info != NULL); |
| 84 | |
| 85 | /* |
| 86 | * TODO: this might require locking the spmc_ep_info structure, |
| 87 | * or provisioning one structure per cpu |
| 88 | */ |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 89 | if (ctx->secondary_ep.entry_point == 0UL) { |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 90 | goto exit; |
| 91 | } |
| 92 | |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 93 | spmc_ep_info->pc = ctx->secondary_ep.entry_point; |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 94 | cm_setup_context(&ctx->cpu_ctx, spmc_ep_info); |
| 95 | write_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), CTX_GPREG_X0, |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 96 | ctx->secondary_ep.context); |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 97 | |
| 98 | /* Mark CPU as initiating ON operation */ |
| 99 | ctx->state = SPMC_STATE_ON_PENDING; |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 100 | |
| 101 | rc = spmd_spm_core_sync_entry(ctx); |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 102 | if (rc != 0ULL) { |
| 103 | ERROR("%s failed (%llu) on CPU%u\n", __func__, rc, |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 104 | linear_id); |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 105 | ctx->state = SPMC_STATE_OFF; |
| 106 | return; |
| 107 | } |
| 108 | |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 109 | exit: |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 110 | ctx->state = SPMC_STATE_ON; |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 111 | |
| 112 | VERBOSE("CPU %u on!\n", linear_id); |
| 113 | } |
| 114 | |
| 115 | /******************************************************************************* |
| 116 | * spmd_cpu_off_handler |
| 117 | ******************************************************************************/ |
| 118 | static int32_t spmd_cpu_off_handler(u_register_t unused) |
| 119 | { |
| 120 | spmd_spm_core_context_t *ctx = spmd_get_context(); |
| 121 | unsigned int linear_id = plat_my_core_pos(); |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 122 | int64_t rc; |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 123 | |
| 124 | assert(ctx != NULL); |
| 125 | assert(ctx->state != SPMC_STATE_OFF); |
| 126 | |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 127 | if (ctx->secondary_ep.entry_point == 0UL) { |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 128 | goto exit; |
| 129 | } |
| 130 | |
| 131 | /* Build an SPMD to SPMC direct message request. */ |
| 132 | spmd_build_spmc_message(get_gpregs_ctx(&ctx->cpu_ctx), PSCI_CPU_OFF); |
| 133 | |
| 134 | rc = spmd_spm_core_sync_entry(ctx); |
Olivier Deprez | 73ef0dc | 2020-06-19 15:33:41 +0200 | [diff] [blame] | 135 | if (rc != 0ULL) { |
| 136 | ERROR("%s failed (%llu) on CPU%u\n", __func__, rc, linear_id); |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /* TODO expect FFA_DIRECT_MSG_RESP returned from SPMC */ |
| 140 | |
| 141 | exit: |
| 142 | ctx->state = SPMC_STATE_OFF; |
| 143 | |
| 144 | VERBOSE("CPU %u off!\n", linear_id); |
| 145 | |
| 146 | return 0; |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | /******************************************************************************* |
| 150 | * Structure populated by the SPM Dispatcher to perform any bookkeeping before |
| 151 | * PSCI executes a power mgmt. operation. |
| 152 | ******************************************************************************/ |
| 153 | const spd_pm_ops_t spmd_pm = { |
| 154 | .svc_on_finish = spmd_cpu_on_finish_handler, |
Olivier Deprez | c7631a5 | 2020-03-23 09:53:06 +0100 | [diff] [blame] | 155 | .svc_off = spmd_cpu_off_handler |
Olivier Deprez | be67111 | 2019-10-28 09:07:50 +0000 | [diff] [blame] | 156 | }; |