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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz430147a2016-02-22 16:44:41 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35/ {
36};
37
38/ {
39 model = "FVP Base";
40 compatible = "arm,vfp-base", "arm,vexpress";
41 interrupt-parent = <&gic>;
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 chosen { };
46
47 aliases {
48 serial0 = &v2m_serial0;
49 serial1 = &v2m_serial1;
50 serial2 = &v2m_serial2;
51 serial3 = &v2m_serial3;
52 };
53
54 psci {
Soby Mathew1df077b2015-01-15 11:49:58 +000055 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
Achin Gupta4f6ad662013-10-25 09:08:21 +010056 method = "smc";
57 cpu_suspend = <0xc4000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0xc4000003>;
60 };
61
62 cpus {
63 #address-cells = <2>;
64 #size-cells = <0>;
65
Achin Gupta5ab4fe42014-08-20 17:33:09 +010066 cpu-map {
67 cluster0 {
68 core0 {
69 cpu = <&CPU0>;
70 };
71 core1 {
72 cpu = <&CPU1>;
73 };
74 core2 {
75 cpu = <&CPU2>;
76 };
77 core3 {
78 cpu = <&CPU3>;
79 };
80 };
81
82 cluster1 {
83 core0 {
84 cpu = <&CPU4>;
85 };
86 core1 {
87 cpu = <&CPU5>;
88 };
89 core2 {
90 cpu = <&CPU6>;
91 };
92 core3 {
93 cpu = <&CPU7>;
94 };
95 };
96 };
97
98 idle-states {
99 entry-method = "arm,psci";
100
101 CPU_SLEEP_0: cpu-sleep-0 {
102 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +0100103 local-timer-stop;
104 arm,psci-suspend-param = <0x0010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100105 entry-latency-us = <40>;
106 exit-latency-us = <100>;
107 min-residency-us = <150>;
108 };
109
110 CLUSTER_SLEEP_0: cluster-sleep-0 {
111 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +0100112 local-timer-stop;
113 arm,psci-suspend-param = <0x1010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100114 entry-latency-us = <500>;
115 exit-latency-us = <1000>;
116 min-residency-us = <2500>;
117 };
118 };
119
120 CPU0:cpu@0 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x0>;
124 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000126 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100128
129 CPU1:cpu@1 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130 device_type = "cpu";
131 compatible = "arm,armv8";
132 reg = <0x0 0x1>;
133 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100134 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000135 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100137
138 CPU2:cpu@2 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 device_type = "cpu";
140 compatible = "arm,armv8";
141 reg = <0x0 0x2>;
142 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100143 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000144 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100146
147 CPU3:cpu@3 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148 device_type = "cpu";
149 compatible = "arm,armv8";
150 reg = <0x0 0x3>;
151 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000153 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100155
156 CPU4:cpu@100 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157 device_type = "cpu";
158 compatible = "arm,armv8";
159 reg = <0x0 0x100>;
160 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100161 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000162 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100164
165 CPU5:cpu@101 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166 device_type = "cpu";
167 compatible = "arm,armv8";
168 reg = <0x0 0x101>;
169 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100170 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000171 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100173
174 CPU6:cpu@102 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175 device_type = "cpu";
176 compatible = "arm,armv8";
177 reg = <0x0 0x102>;
178 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100179 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000180 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100182
183 CPU7:cpu@103 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184 device_type = "cpu";
185 compatible = "arm,armv8";
186 reg = <0x0 0x103>;
187 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100188 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000189 next-level-cache = <&L2_0>;
190 };
191
192 L2_0: l2-cache0 {
193 compatible = "cache";
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194 };
195 };
196
197 memory@80000000 {
198 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +0100199 reg = <0x00000000 0x80000000 0 0x7F000000>,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200 <0x00000008 0x80000000 0 0x80000000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201 };
202
Harry Liebel34988592013-11-11 13:24:47 +0000203 gic: interrupt-controller@2f000000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204 compatible = "arm,gic-v3";
205 #interrupt-cells = <3>;
Harry Liebel34988592013-11-11 13:24:47 +0000206 #address-cells = <2>;
207 #size-cells = <2>;
208 ranges;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209 interrupt-controller;
210 reg = <0x0 0x2f000000 0 0x10000>, // GICD
211 <0x0 0x2f100000 0 0x200000>, // GICR
212 <0x0 0x2c000000 0 0x2000>, // GICC
213 <0x0 0x2c010000 0 0x2000>, // GICH
Harry Liebel34988592013-11-11 13:24:47 +0000214 <0x0 0x2c02f000 0 0x2000>; // GICV
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215 interrupts = <1 9 4>;
Harry Liebel34988592013-11-11 13:24:47 +0000216
217 its: its@2f020000 {
218 compatible = "arm,gic-v3-its";
219 msi-controller;
220 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
221 };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222 };
223
224 timer {
225 compatible = "arm,armv8-timer";
226 interrupts = <1 13 0xff01>,
227 <1 14 0xff01>,
228 <1 11 0xff01>,
229 <1 10 0xff01>;
230 clock-frequency = <100000000>;
231 };
232
233 timer@2a810000 {
234 compatible = "arm,armv7-timer-mem";
235 reg = <0x0 0x2a810000 0x0 0x10000>;
236 clock-frequency = <100000000>;
237 #address-cells = <2>;
238 #size-cells = <2>;
239 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100240 frame@2a830000 {
241 frame-number = <1>;
242 interrupts = <0 26 4>;
243 reg = <0x0 0x2a830000 0x0 0x10000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244 };
245 };
246
247 pmu {
248 compatible = "arm,armv8-pmuv3";
249 interrupts = <0 60 4>,
250 <0 61 4>,
251 <0 62 4>,
252 <0 63 4>;
253 };
254
255 smb {
256 compatible = "simple-bus";
257
258 #address-cells = <2>;
259 #size-cells = <1>;
260 ranges = <0 0 0 0x08000000 0x04000000>,
261 <1 0 0 0x14000000 0x04000000>,
262 <2 0 0 0x18000000 0x04000000>,
263 <3 0 0 0x1c000000 0x04000000>,
264 <4 0 0 0x0c000000 0x04000000>,
265 <5 0 0 0x10000000 0x04000000>;
266
267 #interrupt-cells = <1>;
268 interrupt-map-mask = <0 0 63>;
Harry Liebel34988592013-11-11 13:24:47 +0000269 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
270 <0 0 1 &gic 0 0 0 1 4>,
271 <0 0 2 &gic 0 0 0 2 4>,
272 <0 0 3 &gic 0 0 0 3 4>,
273 <0 0 4 &gic 0 0 0 4 4>,
274 <0 0 5 &gic 0 0 0 5 4>,
275 <0 0 6 &gic 0 0 0 6 4>,
276 <0 0 7 &gic 0 0 0 7 4>,
277 <0 0 8 &gic 0 0 0 8 4>,
278 <0 0 9 &gic 0 0 0 9 4>,
279 <0 0 10 &gic 0 0 0 10 4>,
280 <0 0 11 &gic 0 0 0 11 4>,
281 <0 0 12 &gic 0 0 0 12 4>,
282 <0 0 13 &gic 0 0 0 13 4>,
283 <0 0 14 &gic 0 0 0 14 4>,
284 <0 0 15 &gic 0 0 0 15 4>,
285 <0 0 16 &gic 0 0 0 16 4>,
286 <0 0 17 &gic 0 0 0 17 4>,
287 <0 0 18 &gic 0 0 0 18 4>,
288 <0 0 19 &gic 0 0 0 19 4>,
289 <0 0 20 &gic 0 0 0 20 4>,
290 <0 0 21 &gic 0 0 0 21 4>,
291 <0 0 22 &gic 0 0 0 22 4>,
292 <0 0 23 &gic 0 0 0 23 4>,
293 <0 0 24 &gic 0 0 0 24 4>,
294 <0 0 25 &gic 0 0 0 25 4>,
295 <0 0 26 &gic 0 0 0 26 4>,
296 <0 0 27 &gic 0 0 0 27 4>,
297 <0 0 28 &gic 0 0 0 28 4>,
298 <0 0 29 &gic 0 0 0 29 4>,
299 <0 0 30 &gic 0 0 0 30 4>,
300 <0 0 31 &gic 0 0 0 31 4>,
301 <0 0 32 &gic 0 0 0 32 4>,
302 <0 0 33 &gic 0 0 0 33 4>,
303 <0 0 34 &gic 0 0 0 34 4>,
304 <0 0 35 &gic 0 0 0 35 4>,
305 <0 0 36 &gic 0 0 0 36 4>,
306 <0 0 37 &gic 0 0 0 37 4>,
307 <0 0 38 &gic 0 0 0 38 4>,
308 <0 0 39 &gic 0 0 0 39 4>,
309 <0 0 40 &gic 0 0 0 40 4>,
310 <0 0 41 &gic 0 0 0 41 4>,
311 <0 0 42 &gic 0 0 0 42 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100312
Juan Castillo4dc4a472014-08-12 11:17:06 +0100313 /include/ "rtsm_ve-motherboard-no_psci.dtsi"
Achin Gupta4f6ad662013-10-25 09:08:21 +0100314 };
315
316 panels {
317 panel@0 {
318 compatible = "panel";
319 mode = "XVGA";
320 refresh = <60>;
321 xres = <1024>;
322 yres = <768>;
323 pixclock = <15748>;
324 left_margin = <152>;
325 right_margin = <48>;
326 upper_margin = <23>;
327 lower_margin = <3>;
328 hsync_len = <104>;
329 vsync_len = <4>;
330 sync = <0>;
331 vmode = "FB_VMODE_NONINTERLACED";
332 tim2 = "TIM2_BCD", "TIM2_IPC";
333 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
334 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
335 bpp = <16>;
336 };
337 };
338};